Abstract: A fault-tolerant computer system includes a plurality of redundant processor cores configured to simultaneously execute identical sets of processor-executable instructions, and a coprocessor component including a data storage component and a configurable logic region, where the plurality of processor cores are configured with processor-executable instructions to perform operations including configuring the configurable logic region of the coprocessor component with a first coprocessing module, and controlling the first coprocessing module to perform first processing operations on data located in the data storage component. In various embodiments, the redundant processor cores and the coprocessor component may be implemented on an FPGA, and the redundant processor cores may be configured to swap out different coprocessing modules using Partial Reconfiguration (PR) to perform data processing algorithms using hardware acceleration.
Type:
Grant
Filed:
November 18, 2024
Date of Patent:
April 29, 2025
Assignees:
MONTANA STATE UNIVERSITY, RESILIENT COMPUTING, LLC
Inventors:
Brock Jerome LaMeres, Christopher Michel Major, Hezekiah Ajax Austin
Abstract: A computer device including a computing engine having a plurality of processor cores configured to simultaneously execute identical sets of processor-executable instructions, where each of the processor cores includes different instruction code assignments, and a malware monitoring and remediation component that detects presence of malware when instruction register values from a predetermined number of processor cores are identical during an instruction cycle. In various embodiments, the computer device may be an “edge” computer deployed in military or other highly-sensitive environments. The computing engine may be implemented using one or more field programmable gate arrays (FPGAs).
Type:
Grant
Filed:
February 15, 2024
Date of Patent:
July 30, 2024
Assignees:
MONTANA STATE UNIVERSITY, RESILIENT COMPUTING, LLC
Inventors:
Brock Jerome Lameres, Christopher Michel Major, Clemente I. Izurieta
Abstract: A fault-tolerant computer system includes a plurality of processors configured to simultaneously execute identical sets of processor-executable instructions, each of the plurality of processors containing a processor core including one or more registers and a local memory, an arbiter configured to read each of the registers of the plurality of processors, detect incorrect register values, and overwrite the registers containing the incorrect register values with corrected register values, and a memory scrubber configured to read each address of the local memories of the plurality of processors, detect incorrect memory values, and overwrite addresses containing the incorrect memory values with corrected memory values. In various embodiments, the computer system may be implemented using one or more field programmable gate arrays (FPGAs).
Type:
Grant
Filed:
October 10, 2023
Date of Patent:
April 23, 2024
Assignees:
MONTANA STATE UNIVERSITY, RESILIENT COMPUTING, LLC
Inventors:
Brock J. Lameres, Christopher Michel Major