Abstract: Techniques to improve the operating speed and switching performance of a latch having an integrated gate. In one design, the latch includes first and second differential amplifiers and a feedback circuit (e.g., a third differential amplifier). The first differential amplifier has a number of non-inverting inputs (e.g., configured to implement an OR function) and an inverting input, receives and senses input signals applied to the non-inverting inputs during a “sensing” phase, and provides a differential output. The second differential amplifier latches the output during a “latching” phase. The feedback circuit detects the non-inverting output and provides a control signal for the inverting input of the first differential amplifier. The feedback circuit can provide positive feedback, and can dynamically adjust the inverting input to provide improved switching performance.

Abstract: A logic gate that includes a first differential amplifier and a feedback circuit. The first differential amplifier has a number of first (e.g., non-inverting) inputs and a second (e.g., inverting) input, receives and senses input signals applied to the non-inverting inputs, and provides a differential output that is a particular logic function (e.g., an ‘OR’) of the input signals. The non-inverting inputs may correspond to the gates of a number of transistors coupled in parallel to form an OR function. The feedback circuit detects the (e.g., non-inverting node of the) differential output and provides a control signal for the inverting input of the first differential amplifier. The logic gate typically further includes a second differential amplifier that senses and further drives the differential output.

Abstract: Various methods and apparatus for frequency-domain estimation of carrier frequency offsets are provided in which the carrier frequency offset estimate is robust against non-white (frequency-dependent) noise. A carrier-specific weighting factor is associated with each carrier of a multi-carrier signal. Using the carrier-specific weighting factors, a carrier frequency offset estimate is computed from received signals and estimated channel transfer functions associated with each of the carriers. Because greater weights are given to carriers whose frequencies include lower noise and/or carriers transmitting a known sequence of symbols, the estimate of the carrier frequency offset is improved. The carrier frequency offset estimate may then be applied in a feedback loop to phase-compensate a subsequently received signal.

Abstract: Various methods and systems efficiently implement broadband multi-carrier communication systems. The invention exploits the structural properties of a frequency-domain channel estimator and transforms it into the time domain. This allows the sharing of certain blocks of hardware (e.g., matched filters otherwise used for timing acquisition) which results in significant reduction of complexity.

Abstract: Various circuits and methods provide for dc offset reduction that is effective under varying circuit and signal conditions. The offset signal is first sampled and stored, and then subtracted from the signal path via a programmable transconductance amplifier that is placed in a feedback loop during offset reduction. By designing the transconductance amplifier to have programmable gain, the offset reduction technique is capable of compensating for variations in the magnitude of the offset signal. In one embodiment, an amplifier is placed in the feedback path in series with the programmable transconductance amplifier to optimize the trade off between noise and accuracy of offset reduction.

Abstract: A method for measuring a difference in DC offsets associated with different gain settings in a direct conversion receiver having a variable gain is provided. In a first phase, a set of response parameters that characterize a time-dependent system response to a known change in the DC offset is determined. Each response parameter corresponds to the response measured at a different time after the change. In a second phase, different gain settings are applied to the system and the response is measured at times corresponding to the times associated with each of the response parameters. The response parameters are then used to determine the difference in DC offsets associated with the different gain settings.

Abstract: A local oscillator architecture provides a signal at an output frequency with reduced pulling effect. A voltage controlled oscillator (VCO) generates a first signal having a frequency that is a fraction of the output frequency. A frequency shifter generates a second signal with a frequency substantially equal to the difference between the VCO frequency and the output frequency. Single-sideband mixers are used to produce output signals at the sum of the VCO frequency and the shifted frequency while suppressing an unwanted sideband at the difference of the two frequencies.

Abstract: A mixer circuit of the present invention includes a gain stage configured to receive a first signal and a modulated bias current, and in accordance therewith, produce an output signal, the gain stage generating a first current and receiving the modulated bias current from a bias circuit on a common node. The bias circuit includes an input configured to receive a second signal, and in accordance therewith, generate the modulated bias current. The mixer circuit also includes a current shunt circuit for generating a second current. The first current, the second current, and the modulated bias current are coupled to the common node. In one embodiment, the first signal is approximately a square wave, and the frequency of the first signal is one-third the frequency of the second signal.

Abstract: Various circuits and methods provide for dc offset reduction that is effective under varying circuit and signal conditions. The offset signal is first sampled and stored, and then subtracted from the signal path via a programmable transconductance amplifier that is placed in a feedback loop during offset reduction. By designing the transconductance amplifier to have programmable gain, the offset reduction technique is capable of compensating for variations in the magnitude of the offset signal. In one embodiment, an amplifier is placed in the feedback path in series with the programmable transconductance amplifier to optimize the trade off between noise and accuracy of offset reduction.