Abstract: A capacitor comprising: a metal plate a doped semiconductor plate; and a dielectric sandwiched therebetween.

Abstract: A semiconductor structure having an electrically conducting silicon substrate and a GaN semiconductor device separated from the substrate by a buffer layer is provided. The buffer layer electrically connects the silicon substrate with the GaN semiconductor device. In addition, a GaN LED arranged in a flip chip orientation on the buffer layer on the substrate is provided.

Abstract: A reflecting light emitting structure includes a substrate having a plurality of grooves formed in a first face of the substrate is disclosed. The first face is in a first crystallographic plane. Each of the plurality of grooves includes a first sidewall that is coplanar with a second crystallographic plane and a second sidewall that is coplanar with a third crystallographic plane. A buffer layer is provided on the substrate to reduce mechanical strain between the substrate and a light emitting diode (LED) fabricated on the buffer layer.

Abstract: A field effect transistor comprising a semiconductor substrate comprising an electrically conducting channel layer therein; a plurality of source and drain fingers on a first face of the substrate, each finger separated from the adjacent finger by a gate channel; the gate channels comprising at least one active gate channel defined by a source finger and a drain finger arranged on the first face such that current is free to flow between them via the electrically conducting channel layer, and, a plurality of inactive gate channels, each inactive gate channel being defined by either two fingers of the same type or a source finger and a drain finger, the source finger and drain finger being arranged on the first face such that current is not free to flow between them via the electrically conducting channel layer; the gate channels being arranged such that each active gate channel has a gate channel on each side; each active gate channel comprising a gate therein for controlling current flow in the electrically c

Abstract: A compound field effect transistor having multiple pinch-off voltages, comprising first and second field effect transistors, each field effect transistor comprising a semiconductor layer, the semiconductor layer having an electrically conducting layer therein. An ohmic contact layer on the semiconductor layer, a source and a drain on the ohmic contact layer, at least one gate on the semiconductor layer between source and drain, at least one gate of the first transistor and one gate of the second transistor being matched gates, each gate having the same effective thickness of electrically conducting layer beneath it, but the gates having different gate lengths.

Abstract: A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; wherein the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode.

Abstract: A heterojunction bipolar transistor comprising a substrate; a collector on the substrate; a base layer on the collector; an emitter layer on the base layer; the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and base; the collector, base and emitter layers being npn or pnp doped respectively; characterized in that the lower emitter layer has a larger bandgap than the base layer and is AlxIn1-xP or GaxAl1-xP, x being in the range 0+ to 1.

Abstract: A compound field effect transistor having multiple pinch-off voltages, comprising first and second field effect transistors, each field effect transistor comprising a semiconductor layer, the semiconductor layer having an electrically conducting layer therein. An ohmic contact layer on the semiconductor layer, a source and a drain on the ohmic contact layer, at least one gate on the semiconductor layer between source and drain, at least one gate of the first transistor and one gate of the second transistor being matched gates, each gate having the same effective thickness of electrically conducting layer beneath it, but the gates having different gate lengths.

Abstract: A transistor includes a first electrode on a substrate, wherein the first electrode comprises a bus bar and has first and second first electrode fingers extending therefrom, the fingers being spaced apart to define a channel therebetween. The transistor also includes a second electrode on the substrate having a second electrode finger spaced apart from the first electrode and extending along the channel to define a gate region between the fingers. The gate region comprises a “curved” portion beyond the end of the second electrode finger proximate to the bus bar of the first electrode and a gate electrode extends along the gate region, through the “curved” gate portion. The substrate further comprises an active layer beneath the gate region, characterized in that the active layer extends beyond the end of the second electrode finger beneath the “curved” portion of the gate region.

Abstract: A reflecting light emitting structure includes a substrate having a plurality of grooves formed in a first face of the substrate is disclosed. The first face is in a first crystallographic plane. Each of the plurality of grooves includes a first sidewall that is coplanar with a second crystallographic plane and a second sidewall that is coplanar with a third crystallographic plane. A buffer layer is provided on the substrate to reduce mechanical strain between the substrate and a light emitting diode (LED) fabricated on the buffer layer.

Abstract: A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; wherein the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode.

Abstract: A compound field effect transistor having multiple pinch-off voltages comprising: first and second field effect transistors, each field effect transistor comprising a semiconductor layer, the semiconductor layer having an electrically conducting layer therein; an ohmic contact layer on the semiconductor layer; a source and a drain on the ohmic contact layer; at least one gate on the semiconductor layer between source and drain; at least one gate of the first transistor and one gate of the second transistor being matched gates, each gate having the same effective thickness of electrically conducting layer beneath it but the gates having different gate lengths.

Abstract: A light emitting structure having reverse voltage protection (RVP) is provided along with disclosure of a method for fabricating the light emitting structure. The light emitting structure includes a substrate having a first face, a second face, and a p-n junction formed within the substrate between a p-type layer and an n-type layer, wherein the p-type layer and the n-type layer are adapted as a RVP diode. A buffer layer is provided on the substrate, and a light emitting diode (LED) is fabricated on the buffer layer. The LED is then electrically coupled to the RVP diode in an anti-parallel diode pair (APDP) configuration.

Abstract: A method of correcting for pattern run out in a desired pattern in directional deposition or etching comprising the steps of providing a test substrate; providing a stencil of known thickness on the test substrate; providing a stencil pattern extending through the stencil to the test substrate.

Abstract: A multigate Schottky diode comprising an electrically conducting active semiconductor region; first and second electrically connected metallic contact arms on the active semiconductor region forming ohmic contacts therewith; the ohmic contacts being spaced apart on the active semiconductor region to define a gate receiving channel therebetween. a plurality of electrically connected metallic gate fingers, the metallic gate fingers being in contact with the active semiconductor region to form Schottky junctions, the Schottky junctions being spaced apart on the active semiconductor region and extending at least partially along the gate receiving channel.

Abstract: A semiconductor structure having an electrically conducting silicon substrate and a GaN semiconductor device separated from the substrate by a buffer layer is provided. The buffer layer electrically connects the silicon substrate with the GaN semiconductor device. In addition, a GaN LED arranged in a flip chip orientation on the buffer layer on the substrate is provided.

Abstract: A diode assembly comprising first and second diodes each having a different breakdown voltage, each of the first and second diodes comprising a semiconductor substrate; an electrically conducting channel layer on the semiconductor substrate; an upper semiconductor layer on the channel layer, the upper semiconductor layer comprising a recess; first and second ohmic contacts on the upper semiconductor layer on opposite sides of the recess, the ohmic contacts being connected together to form a first diode contact; a gate electrode within the recess, the gate electrode forming a second diode contact; characterised in that the area of the recess of the first diode covered by the first gate electrode is different to the area of the recess of the second diode covered by the second gate electrode.

Abstract: A field effect transistor comprising a substrate; an electrically conducting channel within the substrate; an electrically conducting source on the substrate comprising a source finger; an electrically conducing drain on the substrate comprising a drain finger; the source and drain fingers being separated to define a path therebetween; at least one electrically conducting source/drain strip extending along the path; at least one rectifying gate strip extending along the path on each side of the source/drain strip, each gate strip being adapted to control the current flow in the conducting channel.

Abstract: A linear antenna switch arm comprising a plurality of field effect transistors connected in series, the drain of each transistor being connected to the source of the next transistor at a join, the end source comprising one of a signal input or output port and the end drain comprising the complementary signal output port or input port; a signal line extending between the input and output ports; at least one of the joins being connected to the signal line at a node by a connection line; the signal line comprising at least one resistor between signal input and output ports; and the connection line comprising at least one resistor.

Abstract: A field effect transistor comprising a semiconductor substrate comprising an electrically conducting channel layer therein; a plurality of source and drain fingers on a first face of the substrate, each finger separated from the adjacent finger by a gate channel; the gate channels comprising at least one active gate channel defined by a source finger and a drain finger arranged on the first face such that current is free to flow between them via the electrically conducting channel layer, and, a plurality of inactive gate channels, each inactive gate channel being defined by either two fingers of the same type or a source finger and a drain finger, the source finger and drain finger being arranged on the first face such that current is not free to flow between them via the electrically conducting channel layer; the gate channels being arranged such that each active gate channel has a gate channel on each side; each active gate channel comprising a gate therein for controlling current flow in the electrically c