Abstract: An improved audio amplifier system can both reduce power consumption by supporting a standby mode and shorten wake time when resuming from the standby mode. The audio amplifier system may reduce power by entering a sleep or standby state in response to a command and/or detecting that an audio input signal is not received. Further, the audio amplifier system may use a burst generator to periodically or intermittently activate the power supply during standby mode. By periodically or intermittently activating the power supply, one or more of the capacitors may be charged. By charging the capacitors during standby mode, the time to wake from standby mode may be significantly reduced. In some cases, the wake time may be reduced by several order of magnitudes (e.g., from seconds to milliseconds).

Abstract: An audio amplifier that implements current mode control without the use of an explicit or separate current mode sensor is disclosed. The audio amplifier may include a pair of feedback loops that provide current from a node located before an inductor of an output filter and current from a node located after the inductor of the output filter to an integrator circuit. The integrator circuit may be formed from existing circuitry of the audio amplifier controller. Thus, current mode control can be implemented without a separate current mode sensor.

Abstract: Aspects disclosed herein eliminate audible disturbances that may occur when an audio amplifier is activated and deactivated. A feedback circuit is used to maintain a closed loop when transistors of a power output stage are activate or deactivated, thereby enabling the charge to build or dissipate without causing an audible disturbance. Further, in certain implementations, the power output stage may remain in an enable state for a period of time after deactivation of the audio amplifier regardless of whether an audio input signal is received enabling dissipation of charge without causing an audible disturbance.

Abstract: A voltage controlled amplifier with an amplitude limiting circuit, such as a clip limiter, that is separate from the signal path on which the input signal is received by a power amplifier can reduce both noise and power expenditure of the voltage controlled amplifier. The amplitude limiting circuit can include a transistor network that is controlled by a pair of utility operational amplifiers. These utility amplifiers may use less current than the audio amplifier of the voltage controlled amplifier. Further, the transistor network can be deactivated when a signal supplied to the voltage controlled amplifier is below a clipping or other voltage limiting threshold.

Abstract: Methods of data encoding using trees formed with logic gates are described which lead to spatial compression of image data. Data encoding is achieved using a five-level wavelet transform, such as the Haar or the 2/10 transform. A dual transform engine is used, the first and engine being used for the first part of the first-level transform, the second part of the first-level transform and the subsequent-level transforms being performed by the second transform engine within a time interval which is less than or equal to the time taken by the first transform engine to effect the part-transform. Each bit plane of the resulting coefficients is then encoded by forming a tree structure from the bits and OR logical combinations thereof. Redundant data are removed from the resulting tree structure, and further data can be removed by using a predetermined compression profile.

Abstract: Methods of data encoding using trees formed with logic gates are described which lead to spatial compression of image data. Data encoding is achieved using a five-level wavelet transform, such as the Haar or the 2/10 transform. A dual transform engine is used, the first and engine being used for the first part of the first-level transform, the second part of the first-level transform and the subsequent-level transforms being performed by the second transform engine within a time interval which is less than or equal to the time taken by the first transform engine to effect the part-transform. Each bit plane of the resulting coefficients is then encoded by forming a tree structure from the bits and OR logical combinations thereof. Redundant data are removed from the resulting tree structure, and further data can be removed by using a predetermined compression profile.

Abstract: A Class D amplifier is described herein that includes an outer loop, an inner loop, and a notch filter. The notch filter can be located between an output of the outer loop and an input of the inner loop. Alternatively or in addition, the notch filter can be located within the outer loop of the Class D amplifier. Ripple content can initially be present at an input to the inner loop of the Class D amplifier, causing nonlinearity in the inner loop and distortion in the audio output signal. The notch filter can filter the ripple content at the input to the inner loop, thereby reducing the nonlinearity present in the inner loop and the distortion in the audio output signal.

Abstract: The present invention is a method and apparatus for adaptively compressing and transmitting streaming video, preferably implemented in hardware as part of a codec, that adaptively applies a variable rate of compression to images in a video stream to optimize the quality attainable for a given transport bandwidth. In one or more embodiments, image frames from the video stream are divided into blocks, and a variable compression ratio compression engine compresses the blocks for transmission over a network. Depending on their compressed sizes, one or more of the compressed blocks are packaged into fixed size data packets for transmission over a network. The data packets are fed into a packet buffer. A packet servo releases packets from the buffer to achieve a desired transport data rate. The amount of compression applied by the compression engine is controlled based on the number of packets in the buffer.

Abstract: A power supply for use with Class D amplifiers in energy efficient applications is described herein. The power supply reduces the effects of off side charging and improves cross regulation. The topology of the power supply can be designed to minimize quiescent mode losses through resonant switching of some or all active switches. Additionally, the power supply can be implemented without external resonant inductors, the power supply can be implemented with smaller capacitors that have longer lifetime ratings, the switching losses present in a power factor correction stage of the power supply can be reduced, and/or a modified power factor correction choke can be utilized to reduce energy loss.

Abstract: Methods of data encoding using trees formed with logic gates are described which lead to spatial compression of image data. Data encoding is achieved using a five-level wavelet transform, such as the Haar or the 2/10 transform. A dual transform engine is used, the first and engine being used for the first part of the first-level transform, the second part of the first-level transform and the subsequent-level transforms being performed by the second transform engine within a time interval which is less than or equal to the time taken by the first transform engine to effect the part-transform. Each bit plane of the resulting coefficients is then encoded by forming a tree structure from the bits and OR logical combinations thereof. Redundant data are removed from the resulting tree structure, and further data can be removed by using a predetermined compression profile.

Abstract: Methods of data encoding using trees formed with logic gates are described which lead to spatial compression of image data. Data encoding is achieved using a five-level wavelet transform, such as the Haar or the 2/10 transform. A dual transform engine is used, the first and engine being used for the first part of the first-level transform, the second part of the first-level transform and the subsequent-level transforms being performed by the second transform engine within a time interval which is less than or equal to the time taken by the first transform engine to effect the part-transform. Each bit plane of the resulting coefficients is then encoded by forming a tree structure from the bits and OR logical combinations thereof. Redundant data are removed from the resulting tree structure, and further data can be removed by using a predetermined compression profile.

Abstract: The present invention is a ceiling-mountable enclosure comprising a support frame, a lightweight inner enclosure, and a back box configured for installation in a suspended ceiling. The apparatus of the present invention includes a removable device door configured to be mounted to the support frame. Electrical and signal wires are routed through conduit access plates provided at the back box. Electrical or other equipment is mounted to a removable device door. The removable device door with mounted equipment is attached to the support frame, then rotated upwards to fit flush with the ceiling and fastened to the support frame. A variety of power receptacles are provided that are configured to be mounted to either the back box, the inner enclosure, or the removable device door. The enclosure includes a cooling system comprising an electrically powered fan and air ducts integrated into the inner enclosure.

Abstract: A cable retractor is provided. In accordance with at least one embodiment, the cable retractor is articulate, comprising an articulate housing which comprises a cable stop housing pivotably coupled to a pulley housing. In accordance with at least one embodiment, the cable retractor also comprises a first pulley assembly coupled to the pulley housing, an end cap coupled to the pulley housing, a spring coupled to the end cap, and a second pulley assembly coupled to the spring. In accordance with at least one embodiment, the first pulley assembly and the second pulley assembly are disposed within the pulley housing. In accordance with at least one embodiment, a cable stop assembly is coupled to the cable stop housing. In accordance with at least one embodiment, the cable retractor is configured to be mountable to a cable access enclosure in a plurality of orientations.

Abstract: The present invention is a speed control for a cable retractor. The cable retractor with which the speed control is used comprises a pulley that engages a cable that may be extended and retracted. A friction element configured to adjustably contact the cable adjacent to the pulley is attached to a movable linkage. The movement of the linkage is constrained to move along a predetermined path such that movement of the linkage along the path alters the distance between the friction element and the pulley. In one or more embodiments a cantilevered spring is attached to the linkage. An adjustable control, for example a thumbscrew, is configured to move the spring in relation to the linkage in a manner that alters the position of the friction element with respect to the cable and/or the pressure exerted by the friction element on the cable.

Abstract: Methods of spatial compression of image data using trees formed with logic gates are described. Data encoding is achieved using a five-level wavelet transform, such as the Haar or 2/10 transforms. A dual transform engine is used, the first engine being used for the first transform, and the subsequent transforms being performed by the second engine. Each bit plane of the resulting coefficients is then encoded by forming a tree structure from the bits and logical OR combinations thereof. Redundant data are removed. Further data can be removed with a predetermined compression profile. The resulting blocks of compressed data are of variable length and are packaged with sync and index words for transmission so that the location and identity of the transformed data blocks can be determined.