Abstract: A method and apparatus for automatic reduction of noise in video signals transmitted over conductors is presented. The present invention provides an adjustable amount of noise filtering matched to the amount of gain provided by an adjustable gain amplifier to a received video signal. One or more stages of a multi-stage discrete gain amplifier is provided with a corresponding noise filter circuit. The filter circuit is matched to the frequency response of and the amount of gain provided by the discrete gain amplifier stage. When the amplifier stage is applied to the received signal, the corresponding noise filter for that stage is invoked as well. In that manner, the amount of noise filtering applied to a video signal automatically varies with the amount of amplification provided to that signal.

Abstract: A method and apparatus for automatic compensation of insertion loss in video signals transmitted over conductors is presented. The present invention is particularly applicable to the transmission of video over long lengths of CAT-5 or similar twisted-pair cables. A reference signal having a known form and strength (e.g. a pulse signal) is provided to each pair of conductors carrying a component of a video signal from a transmitter to a receiver. The receiver includes adjustable gain amplifiers for each conductor pair over which a component of the video signal is transmitted. The gains of the amplifiers are initially set at an initial level (e.g., their maximum gain) to allow detection of the reference signal. Once the reference signal is detected in a conductor pair, the amplifier gains are adjusted such that the level of the reference signal is restored approximately to its original form and strength.

Abstract: The configurable wall mount presented herein has particular applicability to supporting electronic devices mounted in walls and ceilings. The configurability stems from modular components configured to be coupled together. Thus, the wall mount is configurable for mounting devices ranging from small communications connectors to large electronic control panels.

Abstract: A mirrored arc geometrical arrangement of two conductors configured to perform similar functions as a traditional twisted pair of wires is presented. The mirrored arc conductor pair occupies the same physical space required by prior art twisted pair cable designs. Each conductor pair includes two inward-facing arc shaped conductors placed within a dielectric material. Each arc shaped conductor may be constructed from thin foil strips of a conducting metal or from a group of separate bare metal conductors which are placed side by side in intimate contact so as to effectively create the same mirrored arc geometry. The conductor pairs may subsequently be bundled to create a data network cable bundle.

Abstract: The present invention provides lossless switching by configuring the output inductor so that the ripple current amplitude at load conditions results in small negative current during switching. The reconfigured output inductor results in increased ripple current amplitude. This increased ripple amplitude may be further controlled using zero ripple steering techniques to eliminate ripple at the output capacitor. A ripple steering technique involves adding a secondary output to the class D amplifier which steers the switching ripple away from the main output thus substantially relieving the main output from a major artifact of prior art Class D amplifiers.

Abstract: Class D amplifiers are used for their high efficiency, but they have some undesirable characteristics, one of these being the residual switching frequency ripple. Embodiments of the present invention comprise methods and apparatuses for reducing the switching frequency ripple using a technique known herein as ripple steering. A secondary output is added to the amplifier for the purpose of steering the switching ripple away from the main output thus substantially relieving the main output from a major artifact of prior art Class D amplifiers.

Abstract: Class D amplifiers are used for their high efficiency, but they have some undesirable characteristics, one of these being the residual switching frequency ripple. Embodiments of the present invention comprise methods and apparatuses for reducing the switching frequency ripple using a technique known herein as ripple steering. A secondary output is added to the amplifier for the purpose of steering the switching ripple away from the main output thus substantially relieving the main output from a major artifact of prior art Class D amplifiers.

Abstract: A method and apparatus are presented for dynamically testing video equipment. A test pattern utilizes a presentation of alternating pixels and lines, along with features of the electronic video/graphics generator in which it is present to effect a close approximation to the demonstrable contrast transfer function percentage of the system or display under test. The test pattern, while depending on features of the electronic video/graphics generator for convenience of operation, may also be modified to be used as a static pattern capable of very similar utility.

Abstract: This invention describes a method and apparatus for vertically locking input and output video frame rates. The output vertical sync pulse is locked in phase with the input vertical sync pulse, regardless of the input format and frequency. The output resolution, horizontal refresh rate, and delay are all user selectable. Two Phase Locked Loops are connected in series to achieve vertical lock between the input and output frames. Locking the vertical sync pulses between the input and output frames will eliminate mixing of pixels from different input frames in one output frame. The first Phase Locked Loop generates the output pixel clock required to satisfy the user's display preferences but may not precisely represent the desired output pixel clock required for frame locking because current Phase Locked Loops use integer dividers. A second Phase Locked Loop adjusts its output, which is the reference frequency to the first Phase Locked Loop, until a lock is achieved.