Abstract: A test system for measuring beam characteristics of a device under test (DUT) is provided. The system comprises a DUT, a measurement antenna configured to receive electro-magnetic radiation emitted by the DUT, a link antenna configured to provide a test communication link to the DUT, and a control and analyzing unit configured to control a beam steering of the device under test and to analyze signals from the device under test received by the measurement antenna. The test communication data transmitted to the device under test comprises beam steering control data in order to control the beam steering of the DUT.

Abstract: A measuring device provides a central data-processing unit, a control unit and at least one memory unit. The control unit and the at least one memory unit are connected to the central data-processing unit. At a given time, the control unit compares the adjustable parameters of the measuring device with parameters for a basic setting of the measuring device and generates control commands for the adjustment of the deviating parameters, or the control unit registers the parameter changes from a given time and generates control commands from these in order to adjust the changed parameters.

Abstract: A measuring instrument for testing mobile-radio relay stations provides at least one first measuring device and a receiver device. The first measuring device generates a first signal and transmits it either directly or via at least one further device to a relay station under test. The receiver device receives from the relay station under test a second signal derived from the first signal. The first measuring device compares the first signal and at least one signal derived from the second signal.

Abstract: The circuit arrangement according to the invention provides a substrate (10), a connecting element (18) and a chip (16). The substrate (10) provides at least a partial metallisation (11) on its surface. The connecting element (18) is applied to the metallisation (11). The chip (16) is applied to the connecting element (18). The connecting element (18) provides an electrically non-conductive glass layer (14), which is applied directly to the metallisation (11), and an adhesive layer (15) between the chip (16) and the glass layer (14).

Abstract: A radio communications system having a processing circuit, comprising a freely programmable logic control and processing receiving signals and transmission signals. The programming of the freely programmable logic control is modified in order to adjust the same to the sending operation and the receiving operation. Said modification carried out by charging and discharging the functional blocks in the freely programmable logic control via a bus system. The adjustment occurs without any interruption of the function of the radio communications system.

Abstract: A directional coupler provides at least two coupled lines, at least three ports and at least one inductor. A high-frequency signal is transmitted from the first coupled line to the second coupled line. The circuit is constructed in stripline technology. In this context, the second coupled line provides a forward path and a return path, which are connected to a port. An inductor is connected in series to the return path.

Abstract: A circuit for signal conditioning including a first stage with a digital/analog converter, a second stage with an I/Q-modulator, and at least one third stage with a mixer. Instead of a multiplicity of independent oscillators, a shared oscillator is provided for the first, second, and third stages, from an output signal of which a respective oscillator signal and clock-pulse signal for each stage of the first, second, and third stages is derived. The oscillator signal and respective clock-pulse signal of the oscillator are supplied via a frequency divider to at least one stage of the first, second, and third stages, or the oscillator signal of the oscillator is supplied via a frequency multiplier to at least one stage. Also, the oscillator signal of the oscillator is supplied as a reference signal to a frequency synthesizer of at least one stage of the first, second, and third stages.

Abstract: An apparatus for the phase synchronization of several devices, wherein one device is the master device and the other devices are slave devices, with a phase synchronization unit for every device, each of which has: a first controlled oscillator for producing a master reference signal, a first phase detector which, in order to control the first oscillator, compares the phase of a first comparison signal derived from the master reference signal with the phase of a second comparison signal derived from an auxiliary reference signal if the device is itself the master device and a second phase detector which, in order to control the first oscillator, compares the phase of a third comparison signal derived from the master reference signal with the phase of a reference signal coming from the phase synchronization unit of the master device if the device is not itself the master device but a slave device.

Abstract: An attenuator system for adjusting the output of an HF signal source is described in which, between the signal source and an output, an electronic attenuator is disposed via mechanical switches on the input and output side. The mechanical switches can be switched in such a manner that, in one switch position, the electronic attenuator is inserted between the signal source and the output, and in the other switch position, a direct bypass is inserted between the signal source and the output.

Abstract: In order to measure the phase jitter of a high-frequency signal, a spectrum analyzer is used. The high-frequency signal (HF) to be measured is either multiplied by M and/or the output frequency of the variable frequency oscillator of the spectrum analyzer is divided by N, and both signals are set to the same frequency and mixed in a mixer. The output signal of the mixer is then evaluated in the preferably digital evaluating device of the spectrum analyzer according to the Fast Fourier Transformation principle. To this end, the spectrum analyzer requires only one additional mixer, frequency divider and/or frequency multiplier.

Abstract: A base body for a YIG bandpass filter configured from a non-magnetic metal and including filter chambers, which are configured in the base body and contain YIG elements. Cavities and/or radial slots are configured in the base body for the suppression of eddy currents.

Abstract: The described method and calibration unit are used to verify the calibration of a multiport network analyzer which uses a calibration unit for calibration, the unit having a plurality of calibration ports corresponding to the number of measuring ports of the network analyzer, whereby different calibration standards, especially idle, short-circuit, adaptation or through-connection stands can be connected to the calibration ports. According to the inventive method, the calibration ports of the calibration unit art interchanged with the measuring ports of the network analyzer in such a manner that one calibration standard of the calibration unit each which is different from the one used in the previous calibration process is connected to every measuring port of the network analyzer.

Abstract: Procedure for determining length (Lpreamble) of a standard code sequence (preamble) transmitted in a CDMA signal in a defined code channel having a different code class than the code class of the at least one code channel, in which before and/or after the standard code sequence, data are transmitted, includes: (a) determining a chip sequence of the CDMA signal corresponding to an assumed hypothetical length (Lhyp) of the standard code sequence; (b) generating a symbol-sequence by decoding the chip sequence; (c) determining an estimated value of the performance ({circumflex over (P)}hyp) of the symbol sequence; (d) determining whether the estimated value of the performance ({circumflex over (P)}hyp) of the symbol sequence of the assumed hypothetical length (Lhyp) of the standard code sequence understeps a predetermined threshold value; and (e) deciding that the standard code sequence is correct when ({circumflex over (P)}hyp) understeps the predetermined threshold value.

Abstract: A signal analyzer and a method for displaying power levels of code channels of a CMDA signal sent with orthogonal transmit diversity (OTD) via at least one of at least two antennae is described. Once a code class has been determined for representing the power of each individual code channel, the power levels of the code channels in the next highest code class are defined and associated with a respective antenna. Once a code channel exchange has been carried out according to the actual association of the antennae in relation to the code class of the actually active code channels, the power levels of the code channels for at least one antenna are correctly represented on a display device in terms of the antenna.

Abstract: According to the invention, in order to equalise and demodulate a data signal transmitted to a receiver via a time-variant channel, the scatterer coefficients (damping, delay and Doppler frequency) causing the signal distortions in the channel are determined from the received data signal in the receiver. In this way, the data signal id equalised and then demodulated.

Abstract: The invention concerns a procedure for the determination of the length (Lpreamble) of a standard code sequence (preamble), which is transmitted in a CDMA signal in a defined code channel, which has a different code class than the code class of the at least one code channel, in which before and/or after the standard code sequence, data are transmitted, and said procedure has the following steps:

Abstract: A digital compensation filtering technique is provided that enables indirect phase locked loop modulation with a digital modulation data stream having a bandwidth that exceeds, perhaps by an order of magnitude, the bandwidth characteristic of the phase locked loop. A modulation data receiver is provided for receiving from a modulation source digital input modulation data having a bandwidth that exceeds the cutoff frequency characteristic of the phase locked loop frequency response. A digital processor is coupled to the modulation data receiver for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency.

Abstract: To reduce linearity error influences in a HF circuit, particularly in an A/D converter, an input signal of the circuit is multiplied by a first auxiliary signal, and an output signal of the circuit is multiplied by a second auxiliary signal, the first and second auxiliary signals being selected such that a harmonic spectrum of the circuit is broadened.

Abstract: In an apparatus for setting individual different electronic devices of an equipment system for measuring or detecting the properties of a selected object, a control computer is provided for cooperating with a device memory and an object memory. The device memory stores therein the individual devices of the system with their technical properties and their settable functions, while the object memory stores therein. The various object types with their properties. The control computer is configured such that, prior to performing an object measurement or detection, all object types with their properties and also the possible ways of display of these object properties are initially displayed on the screen of the control computer and the user may select therefrom the type of object to be measured or detected and the desired way(s) of displaying said properties.