Abstract: Methods are disclosed to make an anti-fuse PROM which can be embedded into a conventional CMOS process with few additional processing steps and a small additional area for the write circuitry. Nominal, low voltage transistors are used to program the PROM such that these transistor remain functional some time after programming for the purposes of verifying functionality of the memory's programming code. Once the program code has been verified a low cost production version of the part can be instantly made using standard ROM mask programming.

Abstract: Methods are disclosed in making a multi-state dynamic memory using a three transistor cell. The cell construction is consistent with a logic semiconductor process and is therefore useful for embedded memory applications. Considerations are given to write levels, read levels, reference devices, and sense amplifier design. Two cell enhancements are proposed: substituting a PFET in place of and NFET for the write select transistor so that improved noise margin can be achieved and adding a capacitor for extended refresh times. Methods are also introduced to reduce select transistor leakage current during the deselected state.

Abstract: A semiconductor memory architecture is disclosed which results in reduced power dissipation. This reduction is accomplished by partitioning the word line of an array into segments thereby forming selectable blocks within the array. The power is reduced by the number of blocks by which the array can be partitioned. The word line segments are routed to a central decoder with a block select provision. Routing is accomplished with interconnect lines which are typically metal layers. The array remains continuous in spite of block partitioning.