Abstract: A test structure includes a dedicated addressing circuit that allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test structure may be configured for wafer, die or package-level testing. The test structure may be integrated on a common die with the test devices in a single package, provided on separate die in a common package, separately packaged chips or in the form of a collection of standard die configured as the test structure. If on separate die, the test and addressing circuitry is fabricated from a more mature fabrication process than that being characterized for the devices under test. The processes being characterized may be unqualified whereas the test circuitry may be fabricated with different and more mature or qualified processes.

Abstract: A test chip, system and method for testing large numbers of test devices on a single test chip decreases the time and complexity required to characterize the variation and reliability of the IC fabrication process. A remotely configurable test chip can be programmed with varying bias conditions for testing of process variation or numerous failure modes on large sample sizes. An on-chip addressing technique allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test chip may be configured for wafer, die or package-level testing.

Abstract: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.

Abstract: An apparatus and method for detecting and classifying in real-time characteristic of a system component is provided. A sensor senses the system component and outputs a first quantity of data corresponding to a characteristic of the system component. A modeler receives the first quantity of data, converts it to a numerical value and runs a computer model simulation to detect an anomalous behavior of the system component. The detected anomalous behavior is optimized and expressed as a second quantity of data. An autonomous reasoner collects the second quantity of data. A database has a plurality of signatures related to predominant modes of the system component. The autonomous reasoner compares the second quantity of data with the signatures and identifies a signature that matches the second quantity of data. An output indicative of a cause of the anomalous behavior of the system component is provided.

Abstract: The system includes a current injection device in electrical communication with the switch mode power supply. The current injection device is positioned to alter the initial, non-zero load current when activated. A prognostic control is in communication with the current injection device, controlling activation of the current injection device. A frequency detector is positioned to receive an output signal from the switch mode power supply and is able to count cycles in a sinusoidal wave within the output signal. An output device is in communication with the frequency detector. The output device outputs a result of the counted cycles, which are indicative of damage to an a remaining useful life of the switch mode power supply.

Abstract: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.

Abstract: The solder-joint integrity of digital electronic packages, such as FPGAs or microcontrollers that have internally connected input/output buffers, is evaluated by applying a time-varying voltage through one or more solder-joint networks to charge a charge-storage component. Each network includes an I/O buffer on the die in the package and a solder-joint connection, typically one or more such connections inside the package and between the package and a board. The time constant for charging the component is proportional to the resistance of the solder-joint network, hence the voltage across the charge-storage component is a measurement of the integrity of the solder-joint network.

Abstract: The system includes a current injection device in electrical communication with the switch mode power supply. The current injection device is positioned to alter the initial, non-zero load current when activated. A prognostic control is in communication with the current injection device, controlling activation of the current injection device. A frequency detector is positioned to receive an output signal from the switch mode power supply and is able to count cycles in a sinusoidal wave within the output signal. An output device is in communication with the frequency detector. The output device outputs a result of the dounted cycles, which are indicative of damage to an a remaining useful life of the switch mode power supply.

Abstract: A prognostic cell is used to predict impending failure of a useful circuit or circuits in a host IC. Increasing the stress on the prognostic cell relative to the useful circuit shifts the failure distribution of the cell along the time axis. The relative amount of time between the useful circuit failure and prognostic cell trigger point is the “prognostic distance”. The prognostic distance is controlled by designing in the excess stress applied in test device(s), by setting the threshold for triggering in the comparison circuit or by both. Prediction accuracy is enhanced by using multiple test devices to oversample the underlying failure distribution and triggering the failure indicator when a certain fraction fail.

Abstract: A die-level process monitor (DLPM) provides a means for independently determining whether an IC malfunction is a result of the design or the manufacturing processing and further for gathering data on specific process parameters. The DLPM senses parameter variations that result from manufacturing process drift and outputs a measure of the process parameter. The DLPM will typically sense the mismatch of process parameters between two or more test devices as a measure of process variation between a like pair of production devices. The DLPM may be used as a diagnostic tool to determine why an IC failed to perform within specification or to gather statistics on measured process parameters for a given foundry or process.

Abstract: A solder-joint detection circuit uses a resistive bridge and a differential detector to detect faults in the solder-joint network both inside and outside the digital electronic package during operation. The resistive bridge is preferably coupled to a high supply voltage used to power the package. Resistors R1 and R2 are connected in series at a first junction between the high and low supply voltages and a resistor R3 is coupled to the high supply voltage and connected in series with the resistance of the solder-network at a second junction. The network is held at a low voltage on the die. The detector compares the sensitivity and detection voltages and outputs a Pass/Fail signal for the solder-joint network.