Abstract: In a general aspect, execution of programs embodying greedy algorithms and, in more particular, to hybrid quantum systems capable of utilizing quantum computing to assist the execution of programs embodying greedy algorithms. In some cases, a method for generating an output of an optimization problem includes causing, via a communication channel, a quantum resource to execute a quantum-based algorithm corresponding to the optimization problem; obtaining, via the communication channel, quantum results based on data generated by the execution of the quantum-based algorithm, the quantum results being indicative of one or more solutions to the optimization problem as determined by the quantum-based algorithm; based on the quantum results, selecting, by a classical computing system, an unassigned element of the output; determining, by the classical computing system, a value for the selected unassigned element of the output; and returning the output with the determined value.

Abstract: In a general aspect, junction properties of tunnel junctions are altered by voltage-assisted annealing processes. In some cases, a method includes obtaining a circuit comprising a tunnel junction, modifying a junction resistance of the tunnel junction by applying a voltage across the tunnel junction, and obtaining a measured value of the junction resistance. The tunnel junction may include a metal and a metal oxide.

Abstract: In a general aspect, a quantum process for execution by a quantum processor is generated. In some instances, test data representing a test output of a quantum process are obtained. The test data are obtained based on a value assigned to a variable parameter of the quantum process. An objective function is evaluated based on the test data, and an updated value is assigned to the variable parameter based on the evaluation of the objective function. The quantum process is provided for execution by a quantum processor, and the quantum process provided for execution has the updated value assigned to the variable parameter.

Abstract: A system and method for randomly accessing pairs of quantum gates associated with any given quantum gate included in a set of quantum instructions allows for the reduction of unitary errors when executing the quantum instructions. The system generates a set of modified quantum instructions using the randomly accessed pair of quantum gates. The modified quantum instructions produce the same result as the unmodified quantum instructions when executed on a quantum processing system that does not introduce error when executing the instructions. Additionally, the modified quantum instructions produce a more accurate result with less error than the unmodified quantum instructions when executed on a quantum processing system that introduces error.

Abstract: A compiler for a gate-based superconducting quantum computer compiles hybrid classical/quantum algorithms for quantum processing cells with different configurations. The compiler inputs the algorithm and outputs code in a target language executable by a quantum processing cell of a quantum processing system that can execute the algorithm. The compiler includes various functionality, such as: parsing, analyzing control flows, addressing, compressing, and translating. The compiler optimizes algorithms in various manners using the functionality. Some optimizations include addressing efficiently, compressing based on simulations, and translating for efficient execution of parametric functions. The compiler may function in the environment of a cloud quantum computing system. The cloud quantum computing system may receive algorithms from remote access nodes for execution on local classical and quantum computing systems.

Abstract: Heat switches are presented herein for controlling a flow of heat between thermal stages of a cryostat. In one aspect, a heat switch for a cryostat includes a thermal linkage configured to simultaneously contact a first thermal stage and a second thermal stage of the cryostat and define a thermal pathway therebetween. The thermal linkage includes a superconducting element disposed along a portion of the thermal pathway that is capable of transitioning between a superconducting state and a non-superconducting state. A thermal conductivity of the superconducting state is lower than a thermal conductivity of the non-superconducting state. Other types of heat switches are presented, including methods for controlling a flow of heat between thermal stages of a cryostat.

Abstract: In a general aspect, a superconducting quantum processing unit (QPU) includes a plurality of multi-layered cap wafers. In some cases, a quantum processing unit includes quantum processor chips attached to multi-layered cap wafers. Each of the quantum processor chips includes a plurality of qubit devices. The multi-layered cap wafers are configured to provide communication between the quantum processor chips and a control system. Each of the multi-layered cap wafers includes a respective wafer stack that includes a plurality of layers. The plurality of layers of each respective wafer stack includes a first end layer residing closest to a respective quantum processor chip; a second end layer residing farthest from the respective quantum processor chip; and an intermediate layer residing between the first and second end layers. The intermediate layer includes at least one of: a plurality of Purcell filters, a plurality of reflective attenuators, or a plurality of frequency-specific filters.

Abstract: In a general aspect, hybrid computing systems and hybrid computing methods are described. In some cases, a program to be executed in a hybrid computing system is identified. The hybrid computing system includes a control system that includes a classical processor. The hybrid computing system includes a quantum processor that defines qubits. By operation of the control system, a set of events to execute the program is identified. By operation of the control system, an event schedule that includes resource schedules for the respective qubits is generated. The event schedule is executed in the hybrid computing system. The event schedule, when executed in the hybrid computing system, coordinates operation of the quantum processor and the classical processor.

Abstract: In a general aspect, calibration is performed in a quantum computing system. In some cases, domains of a quantum computing system are identified, where the domains include respective domain control subsystems and respective subsets of quantum circuit devices in a quantum processor of the quantum computing system. Sets of measurements are obtained from one of the domains and stored in memory. Device characteristics of the quantum circuit devices of the domain are obtained based on the set of measurements, and the device characteristics are stored in a memory of the control system. Quantum logic control parameters for the subset of quantum circuit devices of the domain are obtained based on the set of measurements and stored in memory.

Abstract: In a general aspect, a photonic quantum network is disclosed. In some implementations, microwave modes and optical modes are generated on first and second quantum processing units (QPUs) by operation of a first transducer device of the first QPU and a second transducer device of the second QPU. The microwave modes are transmitted within the first and second QPUs from the first and second transducer devices to respective first and second qubit devices. The optical modes are transmitted from the first and second QPUs to an interferometer device. By operation of the interferometer device, output signals are generated on respective output channels based on the optical modes from the first and second QPUs. Based on the output signals detected by operation of photodetector devices coupled to the respective output channels, quantum entanglement transferred to the first and second qubit devices by the microwave modes is identified.

Abstract: In a general aspect, a gate is formed for a quantum processor. In some implementations, an arbitrary program is received. The arbitrary program includes a first sequence of quantum logic gates, which includes a parametric XY gate. A native gate set is identified, which includes a set of quantum logic gates associated with a quantum processing unit. A second sequence of quantum logic gates corresponding to the parametric XY gate is identified, which includes a parametric quantum logic gate. Each of the quantum logic gates in the second sequence is selected from the native gate set. A native program is generated. The native program includes a third sequence of quantum logic gates. The third sequence of quantum logic gates corresponds to the first sequence of quantum logic gates and includes the second sequence of quantum logic gates. The native program is provided for execution by the quantum processing unit.

Abstract: In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.

Abstract: In a general aspect, a computer system includes a low-latency communication link between a classical computer and a quantum computing resource. In some cases, a quantum machine image operates on a classical computer system. The quantum machine image includes a virtualized execution environment for quantum programs. The quantum machine image is engaged with a quantum processing unit of a quantum computing system. A quantum program is communicated over a low-latency communication pathway from the classical computer system to the quantum computer system. The quantum program is executed at the quantum computer system.

Abstract: In some aspects, a hybrid quantum-classical computing platform may comprise: a first quantum processor unit (QPU); a second QPU; and a shared classical memory, the shared classical memory being connected to both the first QPU and the second QPU, wherein the shared classical memory is configured to share data between the first QPU and the second QPU. In some embodiments, the first QPU operates at a higher repetition rate and/or clock rate than the second QPU and the second QPU operates with a higher fidelity than the first QPU.

Abstract: In a general aspect, a method of modifying a quantum error correction code for logical qubits is described. In some implementations, a method includes, by operation of classical computing systems, determining target values of logical errors associated with applying operations on logical qubits; by operation of the quantum computing system, measuring observed values of the logical errors associated with applying the operations on the logical qubits; and by operation of the classical computing systems, updating the quantum error correction code based on the target values and the observed values of the logical errors. Updating the quantum error correction code includes modifying a quantum error correction pattern for one or more of the logical qubits. The method further includes, by operation of the quantum computing system, applying the quantum error correction code using the modified quantum error correction pattern while executing a quantum computing routine.

Abstract: In some aspects, a quantum computing system includes a multi-dimensional array of qubit devices. Coupler devices reside at intervals between neighboring pairs of the qubit devices in the multi-dimensional array. Each coupler device is configured to produce an electromagnetic interaction between one of the neighboring pairs of qubit devices. In some cases, each qubit device has a respective qubit operating frequency that is independent of an offset electromagnetic field experienced by the qubit device, and the coupling strength of the electromagnetic interaction provided by each coupler device varies with an offset electromagnetic field experienced by the coupler device. In some cases, readout devices are each operably coupled to a single, respective qubit device to produce qubit readout signals that indicate the quantum state of the qubit device.

Abstract: In a general aspect, a superconducting quantum processing unit (QPU) includes a cap wafer that has multiple connected circuitry portions. In some cases, a QPU includes first and second substrates. The first substrate includes a first surface, a recess, and first superconducting circuitry. The recess is defined by sidewalls and a recessed surface. The recessed surface resides at a depth in the first substrate. The first superconducting circuitry includes a first circuitry portion on the first surface of the first substrate; a second circuitry portion on the recessed surface of the first substrate; and a connection disposed on at least one of the sidewalls and connecting the first and second circuitry portions. The second substrate includes second superconducting circuitry, which includes a quantum circuit device. The first and second substrates are arranged such that the recess forms an enclosure that houses the quantum circuit device.

Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: In a general aspect, a computer system includes a low-latency communication link between a classical computer and a quantum computing resource. In some cases, a quantum machine image operates on a classical computer system. The quantum machine image includes a virtualized execution environment for quantum programs. The quantum machine image is engaged with a quantum processing unit of a quantum computing system. A quantum program is communicated over a low-latency communication pathway from the classical computer system to the quantum computer system. The quantum program is executed at the quantum computer system.

Abstract: In a general aspect, parametric dissipation operations are performed in a quantum computing system. In some implementations, a method includes executing a computer program in a computer system. Executing the computer program includes applying a quantum logic gate associated with a unitary operation to qubits defined by qubit devices on a quantum processing unit; obtaining an estimated value of a dissipation rate parameter; applying a parametric dissipation operation to one or more of the qubit devices; and measuring a state of one or more of the qubit devices. The parametric dissipation operation has a programmable dissipation rate that is controlled by the estimated value of the dissipation rate parameter; and the parametric dissipation operation is applied separately from the quantum logic gate.