Abstract: In some embodiments, a computing system may comprise a memory for storing a ledger; a computer processor for verification of the ledger, wherein the computer processor comprises at least one of a classical computer processor configured to run a virtual quantum machine and a quantum computer comprising a plurality of qubits; wherein the ledger is configured to store arbitrary classical information and quantum information which is verifiable using the computer processor. Furthermore, in some embodiments the computing system is configured to perform operations comprising: adding to the ledger using the computer processor to solve a mathematically difficult problem which is Quantum-Merlin-Arthur-complete (QMA-complete). In embodiments, a blockchain includes a quantum state. In some aspects, a unitary operator corresponding to a quantum rotation is found when new transaction data are to be secured in the blockchain.

Abstract: In a general aspect, a computing system is configured to execute a quantum approximate optimization algorithm. In some aspects, a control system identifies a pair of qubit devices in a quantum processor. The quantum processor includes a connection that provides coupling between the pair of qubit devices. ZZ coupling between the pair of qubit devices is activated to execute a cost function defined in the quantum approximate optimization algorithm. The cost function is associated with a maximum cut problem, and the ZZ coupling is activated by allowing the pair of qubits to evolve under a natural Hamiltonian for a time period ?. One or more of the pair of qubit devices is measured to obtain an output from an execution of the quantum approximate optimization algorithm.

Abstract: In a general aspect, a quantum logic gate is performed in a quantum computing system. In some cases, a pair of qubits are defined in a quantum processor; the pair of qubits can include a first qubit defined by a first qubit device in the quantum processor and a second qubit defined by a tunable qubit device in the quantum processor. A quantum logic gate can be applied to the pair of qubits by communicating a control signal to a control line coupled to the tunable qubit device. The control signal can be configured to modulate a transition frequency of the tunable qubit device at a modulation frequency, and the modulation frequency can be determined based on a transition frequency of the first qubit device.

Abstract: In a general aspect, a photonic quantum network is disclosed. In some implementations, microwave modes and optical modes are generated on first and second quantum processing units (QPUs) by operation of a first transducer device of the first QPU and a second transducer device of the second QPU. The microwave modes are transmitted within the first and second QPUs from the first and second transducer devices to respective first and second qubit devices. The optical modes are transmitted from the first and second QPUs to an interferometer device. By operation of the interferometer device, output signals are generated on respective output channels based on the optical modes from the first and second QPUs. Based on the output signals detected by operation of photodetector devices coupled to the respective output channels, quantum entanglement transferred to the first and second qubit devices by the microwave modes is identified.

Abstract: In a general aspect, information is encoded in data qubits in a three-dimensional device lattice. The data qubits reside in multiple layers of the three-dimensional device lattice, and each layer includes a respective two-dimensional device lattice. A three-dimensional color code is applied in the three-dimensional device lattice to detect errors in the data qubits residing in the multiple layers. A two-dimensional color code is applied in the two-dimensional device lattice in each respective layer to detect errors in one or more of the data qubits residing in the respective layer.

Abstract: In some aspects, a flexible cable may comprise: a flexible strip with first and second parallel surfaces and first and second ends, said flexible strip being electrically insulating; a metal stripline within said flexible strip; first and second metallic grounding planes on said first and second surfaces, respectively; and a first circuit board mechanically attached to at least one of said first end of said flexible strip and said first and second metallic grounding planes at said first end, said first circuit board being mechanically stiff, said metal stripline being electrically connected to electrical circuitry on said first circuit board.

Abstract: In a general aspect, a quantum error-correction technique includes applying a first set of two-qubit gates to qubits in a lattice cell, and applying a second, different set of two-qubit gates to the qubits in the lattice cell. The qubits in the lattice cell include data qubits and ancilla qubits, and the ancilla qubits reside between respective nearest-neighbor pairs of the data qubits. After the first and second sets of two-qubit gates have been applied, measurement outcomes of the ancilla qubits are obtained, and the parity of the measurement outcomes is determined.

Abstract: Heat switches are presented herein for controlling a flow of heat between thermal stages of a cryostat. In one aspect, a heat switch for a cryostat includes a thermal linkage configured to simultaneously contact a first thermal stage and a second thermal stage of the cryostat and define a thermal pathway therebetween. The thermal linkage includes a superconducting element disposed along a portion of the thermal pathway that is capable of transitioning between a superconducting state and a non-superconducting state. A thermal conductivity of the superconducting state is lower than a thermal conductivity of the non-superconducting state. Other types of heat switches are presented, including methods for controlling a flow of heat between thermal stages of a cryostat.

Abstract: In a general aspect, a superconducting via for routing electrical signals through a substrate includes the substrate and a layer formed of superconducting material. The substrate has a first orifice disposed on a first surface and a second orifice disposed on a second surface. A cavity extends through the substrate from the first orifice to the second orifice. The layer of superconducting material includes a first portion occluding the first orifice and having an exterior surface facing outward from the substrate. The layer also includes a second portion in contact with a side wall of the cavity and extending to the second orifice. A quantum circuit element may optionally be disposed on the first surface and electrically coupled to the exterior surface of the first portion of the layer.

Abstract: Interactions between a classical computing system and a quantum computing system can be structured to increase the effective memory available to hold instructions for a quantum processor. The system stores a schedule of compiled quantum processing instructions in a memory storage location on a classical computing system. A small program memory is included in close proximity to a control system for the quantum processor on the quantum computing system. The classical computing system sends a subset of instructions from the schedule of quantum instructions to the program memory. The control system manages execution of the instructions by accessing them at the program memory and configuring the quantum processor accordingly. While the quantum processor executes the instructions, additional instructions are transferred from the classical computing system to the program memory to await execution.