Abstract: A microprocessor having M parallel pipelines and N arithmetic logic units, where N is less than M. A single instruction fetch stage fetches multi-stage instructions, and a single instruction decoder provides a parallel set of three instructions to the three pipelines. The two ALUs are dynamically connected to two of the pipelines having instructions requiring an ALU, while the third pipeline executes an instruction in parallel that does not require an ALU. The third pipeline may have a move unit connected to it.

Abstract: Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions of a typical computer program do not require reading operands from the memory, the probability is high that at least one of any three program instructions to be executed at the same time need not fetch an operand from memory. The two memory ports are thus connected at any given time with the two of the three pipelines which are processing instructions that require memory access, the pipeline without access to the memory processing an instruction that does not need it. To do so, the added third pipeline need not have all the same resources as the other two pipelines, so its stages are made to have a reduced capability in order to save space and reduce power consumption.

Abstract: A write buffer unit operates in a cached memory microprocessor system by dynamically reconfigurable timed flushing of a queue of coalescing write buffers in the unit. Each time an additional one of the coalescing write buffers is allocated, a time-out period is generated which is inversely related to the number of allocated write buffers. After one of the allocated write buffers times out by exceeding the time-out period with no write activity to the coalescing write buffer, a controller in the unit determines the least recently written to allocated write buffer, and generates control signals to flush that write buffer.

Abstract: A control store unit having a control store address generator able to provide both the normal control store address generation functions, and the BIST/logout address generation functions. In response to a test enable signal, the address generator switches between two modes: a normal mode and a test mode. Under the normal mode, normal control store addresses are generated. Under the test mode, a sequence of BIST/logout addresses are generated that sequentially cycles through the entire control store memory at full CPU speed.

Abstract: Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions of a typical computer program do not require reading operands from the memory, the probability is high that at least one of any three program instructions to be executed at the same time need not fetch an operand from memory. The two memory ports are thus connected at any given time with the two of the three pipelines which are processing instructions that require memory access, the pipeline without access to the memory processing an instruction that does not need it. To do so, the added third pipeline need not have all the same resources as the other two pipelines, so its stages are made to have a reduced capability in order to save space and reduce power consumption.

Abstract: A novel method and apparatus of performing data bit moving functions on a data word using two barrel shifters: a left shifter and a right shifter. The present invention is able to handle both shift and rotate functions using one shifter unit. Specifically, for shift functions, only one of the two shifters is used to perform the shifting function. On the other hand, for rotate functions, both shifters are needed for shifting the data word. The amounts of the right shift and left shift depend on the number defined by the count operand and the specific shift/rotate instruction requested.

Abstract: Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions of a typical computer program do not require reading operands from the memory, the probability is high that at least one of any three program instructions to be executed at the same time need not fetch an operand from memory. The two memory ports are thus connected at any given time with the two of the three pipelines which are processing instructions that require memory access, the pipeline without access to the memory processing an instruction that does not need it. To do so, the added third pipeline need not have all the same resources as the other two pipelines, so its stages are made to have a reduced capability in order to save space and reduce power consumption.

Abstract: Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions of a typical computer program do not require reading operands from the memory, the probability is high that at least one of any three program instructions to be executed at the same time need not fetch an operand from memory. The two memory ports are thus connected at any given time with the two of the three pipelines which are processing instructions that require memory access, the pipeline without access to the memory processing an instruction that does not need it. To do so, the added third pipeline need not have all the same resources as the other two pipelines, so its stages are made to have a reduced capability in order to save space and reduce power consumption.

Abstract: Three parallel instruction processing pipelines of a microprocessor share two data memory ports for obtaining operands and writing back results. Since a significant proportion of the instructions of a typical computer program do not require reading operands from the memory, the probability is high that at least one of any three program instructions to be executed at the same time need not fetch an operand from memory. The two memory ports are thus connected at any given time with the two of the three pipelines which are processing instructions that require memory access, the pipeline without access to the memory processing an instruction that does not need it. To do so, the added third pipeline need not have all the same resources as the other two pipelines, so its stages are made to have a reduced capability in order to save space and reduce power consumption.

Abstract: A branch prediction mechanism for predicting the outcome and the branch target address of the next possible branch instruction of a current instruction. Each of the entry of the branch target buffer (“BTB”) of the present invention provides a next possible branch instruction address, and the corresponding branch target address. By checking the TAG portion of each entry of the BTB with the current instruction address, the branch prediction mechanism can predict the next possible branch instruction and the corresponding branch target address.

Abstract: A single chip microprocessor has at least two parallel pipelines that each have multiple processing stages, one of which is an instruction execution stage with a full functioned arithmetic logic unit (ALU). The ALU of one pipeline includes an adder that has the usual two input ports while the adder of the ALU of the other pipeline has at least one extra input port. Two successive arithmetically data dependent instructions are executed by the larger adder alone, while the smaller adder is used as part of a logic circuit that determines the carry bit for the instruction execution result obtained from the larger adder. The smaller adder is thus efficiently used, in an operation where it would otherwise be idle. The additional logic circuitry necessary to determine the carry bit is thus minimized.

Abstract: In a program test of the cache of a microprocessor, a forced hit signal can be set by the CPU. The forced hit signal allows for a more complete testing of the cache. Additionally, a forced write back signal can also be produced. In one embodiment, the forced hit signal will cause the tag RAM to be updated during a write with the forced hit.

Abstract: Improvements are made in how microprocessors execute AND, OR, and TEST instructions when the operands of this instruction are equal. AND/OR/TEST instructions with equal operands are used to set flags based on the contents of the single operand without explicitly performing the actual AND/OR/TEST command. By resetting these flags directly, this mechanism allows these instructions to be paired with preceding dependent instructions simply by using the flags set by the AND/OR/TEST for the previous instruction. An architecture that hardwires the implementation into the microprocessor through logic gates is preferred. This will result in increased speed while reducing power consumption. Further, a full-sized ALU is not needed in order to execute the AND/OR/TEST instruction with equal operands. As this is a more direct procedure, a pipeline with a reduced capability ALU can be utilized.

Abstract: A technique and system for reading instruction data from a cache memory with minimum delays. Addresses are calculated and applied to the cache memory in two or more cycles by a pipelined address generation circuit. While data at one address is being retrieved, the next address is being calculated. It is presumed, when calculating the next address, that the current address will return all the data it is addressing. In response to a miss signal received from the cache when no data at the current address is in the cache, the missed data is read from a main system memory and accessed with improved speed. In a system where the cache memory and processor operate at a higher clock frequency than the main system memory, new data is obtained from the main memory during only periodically occurring cache clock cycles. A missed cache memory address is regenerated in a manner to access such new data during the same cache clock cycle that it first becomes available from the main memory.

Abstract: A novel method and apparatus is disclosed for locating the first most, or least, significant set bit in a bit-string. The present invention breaks down the bit-string into a plurality of shorter sub-strings so that boolean operations can be performed directly to the shorter sub-strings for determining the location of the most/least significant set bit. Furthermore, this method can be repeatedly used to reduce the length of the shorter sub-string after the most/least significant sub-string is located. Particularly, this method of repeatedly dividing the bit-string greatly increases the speed of locating the set bit.