Patents Assigned to Ritsumeikan University
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Patent number: 8495765Abstract: A sock is provided having a first compression area 1 which raises the compressive force in a wale direction from a position A behind the toe area of a sole portion of the sock to a position C which includes the boundary between an arch portion B and a heel portion 6, a second compression area 2 provided on the periphery to raise the compressive force in a course direction at the position A behind the toe area, a third compression area 3 provided on the periphery to raise the compressive force in a course direction at an ankle portion D, and a fourth compression area 4 provided on the periphery to raise the compressive force in a course direction from the position C which includes the boundary between the arch portion B and the heel portion 6 to a position E at the base of the instep portion.Type: GrantFiled: December 23, 2008Date of Patent: July 30, 2013Assignees: Okamoto Corporation, Ritsumeikan UniversityInventors: Takahiro Araki, Yuko Yanagisawa, Masaaki Makikawa
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Patent number: 8082124Abstract: Provided are a data obtaining section (21) that obtains a time-series data fluctuating in accordance with the plasma conditions, a translation error calculation section (24) that calculates a determinism providing an indicator of whether the time-series data in the plasma are deterministic or stochastic, from the time-series data that have been obtained in the data obtaining unit (21), and an abnormal discharge determination section (26) that determines that the plasma is under the abnormal discharge conditions, in the case that the value representing the determinism calculated in the determinism derivation unit is less than or equal to a given threshold value, during the plasma generation. Examples of the value representing the determinism include translation error or permutation entropy. In the case the permutation entropy is used as a value representing the determinism, a permutation entropy calculation section is provided.Type: GrantFiled: July 2, 2007Date of Patent: December 20, 2011Assignees: Ritsumeikan University, Tokyo Electron Ltd.Inventors: Takaya Miyano, Toshiyuki Matsumoto, Naoki Ikeuchi, Tsuyoshi Moriya
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Publication number: 20070131993Abstract: Adjacent pixels in a pixel circuit of an imaging device use a primary capacitance, an amplifying transistor, a reset switch and a selection switch in common. Each pixel has a photodiode and a transfer switch having first and second gates provided on the photodiode side and the primary capacitance side, respectively. In a pixel downsampling read mode, the first and second gate voltages of each pixel to be discarded are brought to high level, and thereafter the first and second gate voltages of each pixel to be read are brought to high level, to transfer charge generated in the photodiode of the pixel to be read to the primary capacitance and the photodiode in each pixel to be discarded. This enables reduction of the potential of the primary capacitance, and hence reduction of the pixel sensitivity than using only the primary capacitance to store charge transferred from the transfer switch.Type: ApplicationFiled: December 13, 2006Publication date: June 14, 2007Applicants: Funai Electric Co., Ltd., Ritsumeikan UniversityInventors: Masaya Oita, Hiromichi Tanaka, Masafumi Kimata, Sumio Terakawa
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Publication number: 20070120982Abstract: In an imaging device having an all-pixel read mode for reading signals from all pixels and a pixel downsampling read mode for reading signals by appropriately discarding pixels, adjacent ones of pixels use a floating diffusion capacitance, an amplifying transistor, a reset switch and a selection switch in common. In the pixel downsampling read mode, not only a primary capacitance but also a photodiode in each pixel to be discarded are used as capacitances for storing signal charges transferred from transfer switches. This makes it possible to lower the gate voltage of the amplifying transistor as compared with the case of using only the primary capacitance as a capacitance for storing signal charges transferred from a transfer switch to reduce the sensitivity of the pixels, thereby reducing the occurrence of flicker.Type: ApplicationFiled: October 27, 2006Publication date: May 31, 2007Applicants: Funai Electric Co., Ltd., Ritsumeikan UniversityInventors: Masaya OITA, Hiromichi Tanaka, Masafumi Kimata
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Publication number: 20060290797Abstract: A solid state imaging device detects the period of energy variation of discharge type illumination, and sets a total exposure time to match the detected period. The total exposure time is divided into alternating valid and invalid exposure times by a division ratio to make the sum of the valid exposure times equal to an actual exposure time corresponding to an actual speed of an electronic shutter. Charges accumulated in a CMOS sensor during the valid exposure times are stored in a floating diffusion, whereas charges accumulated during the invalid exposure times are drained. At the end of the total exposure time, the charges stored during the valid exposure times are converted to an electrical signal which is output to a signal processing circuit. This device can correct variation of output signals which corresponds to the illumination energy variation when the shutter is operated for imaging under high luminance illumination.Type: ApplicationFiled: June 23, 2006Publication date: December 28, 2006Applicants: Funai Electric Co., Ltd., Ritsumeikan UniversityInventors: Hiromichi Tanaka, Hideto Yoshimura, Sumio Terakawa, Masafumi Kimata
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Publication number: 20060273361Abstract: Each of three light receiving sections has a P-type well having a P+-type layer and an N-type layer formed therein. The P+-type layer is diffused from substrate surface to depth d1. A PN junction forming portion of the N-type layer is diffused from depth d1 to depth d2 which is greater than depth d1 so as to form, with the P-type well, a PN junction of a photodiode at depth d2. Depths d1 as well as depths d2 of the three light receiving sections are different from each other. The N-type layer has a charge output portion which is diffused from the PN junction to the substrate surface, and which is coupled by circuit coupling to a MOS transistor for reading out charge. This allows each light receiving section to have spectral characteristics, thereby providing a solid state imaging element and a solid state imaging device without using color filters.Type: ApplicationFiled: June 1, 2006Publication date: December 7, 2006Applicants: Funai Electric Co., Ltd., Ritsumeikan UniversityInventors: Hiromichi Tanaka, Hideto Yoshimura, Sumio Terakawa, Masafumi Kimata