Patents Assigned to RIVERLANE LTD.
  • Patent number: 12001925
    Abstract: A computer-implemented postselection-free method of initializing qubits in a quantum computer, comprising: preparing at least one data qubit and a plurality of auxiliary qubits in respective initial states, wherein each of the at least one data qubit and the plurality of auxiliary qubits has a respective probability of being prepared with an error; and, performing a plurality of non-measurement multi-qubit quantum logic operations that propagate errors between the at least one data qubit and the plurality of auxiliary qubits so as to reduce the probability of an error affecting the at least one data qubit.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: June 4, 2024
    Assignee: RIVERLANE LTD
    Inventors: Ben Barber, Jacob M Taylor, Neil Ian Gillespie
  • Patent number: 11915102
    Abstract: An apparatus for a quantum computer comprising a memory device and a converter block, the memory device comprising: a local command module; and a double-buffer-memory module comprising a plurality of pairs of memory modules, each memory module: coupled to the local command module; and configured to store a respective operation for controlling a qubit of the quantum computer; wherein the local command module is configured to: receive an instruction to provide the operation for the qubit; read the operation from a respective one of the plurality of pairs of memory modules indicated by the instruction; and provide the operation to the converter block; wherein the converter block is configured to receive the operation from the memory device and provide digital output pulses, representative of the operation, to an output interface, the output interface configured to provide the digital output pulses to a digital-to-analogue converter for controlling the qubit to perform the operation.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: February 27, 2024
    Assignee: RIVERLANE LTD
    Inventor: Marco Ghibaudi
  • Patent number: 11914443
    Abstract: A computer-implemented method of selecting a power-optimal compression scheme for transmitting digital control signals from a classical interface of a quantum computer to a quantum processing unit (QPU) of the quantum computer is disclosed. The method involves receiving static and dynamic power consumption values associated with operations performable by the QPU; determining compression schemes implementable by the QPU; calculating total power consumption values associated with receiving and decompressing a representative control signal at the QPU using the compression schemes; and selecting the compression scheme having the lowest total power consumption value. A corresponding method for transmitting control signals from a classical interface of the quantum computer to the QPU is also disclosed in which a compressed control signal is transmitted from the classical interface to the QPU with one or more delays.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: February 27, 2024
    Assignee: RIVERLANE LTD
    Inventors: Richard James Randon Cruise, Robin Clive Sterling, Marco Ghibaudi
  • Patent number: 11901915
    Abstract: A computer-implemented method for decoding syndromes of a quantum error correction code, the syndromes comprising measurement data from a quantum computer, the method comprising: receiving syndrome measurement data comprising a plurality of quantum error correction rounds performed on a plurality of qubits; identifying a plurality of non-overlapping first blocks within the syndrome measurement data, wherein: each first block has: a first central block of quantum error corrections rounds; and a first buffer block of quantum error correction rounds, wherein the first buffer block surrounds the first central block, and each first block is surrounded by an interstitial region of quantum error correction rounds; identifying the location of a first set of errors in the plurality of qubits by decoding each first block to provide respective decoded first central blocks and respective decoded first buffer blocks; outputting the location of the first set of errors contained within each decoded first central block.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: February 13, 2024
    Assignee: RIVERLANE LTD.
    Inventors: Earl Terence Campbell, Luka Skoric