Abstract: A system and method for classification of data units in a network device acts as a bridge in heterogeneous networks, provides many different services and provisions many different transport mechanisms. The data classifier generates an ID that is internally used by the network device in managing, queuing, processing, scheduling and routing to egress the data unit. This internal ID enables the device to accept any type of data units from any physical/logical ports or channels and output those data units on any physical/logical ports or channels that are available. The device utilizes learning on a per-flow basis and can enable the device to identify and process data units used in private line services and private LAN services.

Abstract: The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. It also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. An output terminal is configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements.

Abstract: A search key construction system including search key sections, each coupled to an output of a first multiplexer having a first programmable control, a second multiplexer having a second programmable control and an output coupled to the first multiplexer, and a third multiplexer having a third programmable control and an output coupled to the first multiplexer is disclosed. The first programmable control can include a key source select to enable one of a first type path, a second type path, and a third type path. The first type path can include a designated section position from a packet header, the second type path can include a short field from a packet attribute, and the third type field can include a long field from a packet header.

Abstract: A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: To more fully utilize the available bandwidth of a network link, network nodes in accordance with the present invention allow TDM data to be combined with packet data. A Packet/TDM cross connect switch, having both a TDM switch and a packet switch, is used in these embodiments. Data packets are transformed into TDM packet columns. The TDM packet columns are combined with standard TDM data columns in the payload of a TDM data frame. Data packets may be sorted based on a priority scheme, in which high priority data packets are given precedence over lower priority data. However, both high priority and low priority may be combined in a TDM packet column.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: A feedback reducing device for an acoustic electric guitar is in the form of a plug adapted to be snugly received in the sound hole of a guitar. With the plug in place, the sound hole opening is completely covered and the amplified performance of the instrument is not significantly effected.