Abstract: A logic gate and methods of operation and manufacturing thereof. In one embodiment, the logic gate comprises complementary first and second computational blocks having first and second sets of binary inputs, respectively. The first computational block develops an output binary digit that is a function of a weighted sum of a first set of input binary digits presented at the first set of binary inputs. The second computational block develops a complementary output binary digit that is a function of a weighted sum of a second set of input binary digits presented at the second set of binary inputs. The logic gate further comprises a cross-coupled differential load, including a first load circuit coupled to the first computational block and driven by the complementary output binary digit, and a second load circuit coupled to the second computational block and driven by the output binary digit.

Abstract: A circuit and method for deriving an adder output bit from adder input bits, a multiplier circuit, a method of multiplying, a microprocessor and digital signal processor (DSP) employing the circuit or the method and a method of selecting weights and thresholds for logic gates. In one embodiment, the circuit includes: (1) first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of ones of the adder input bits and (2) combinatorial logic that generates the adder output bit from the intermediate bits. In one embodiment, the multiplier includes a summer having at least two inputs with corresponding weights, the inputs corresponding to bits of a multiplicand, the weights based on a multiplier, the summer generating a weighted sum of the multiplicand that represents a multiplication of the multiplicand and the multiplier that is a function of the weighted sum.

Abstract: A microprocessor and digital signal processor (DSP) are provided. In one embodiment, the microprocessor includes a cache memory and an arithmetic and logic unit that contains at least one of an adder and a multiplier. In another embodiment, the DSP includes a signal input, a signal output and a signal transformation unit containing at least one of an adder and a multiplier. In each embodiment, the at least one includes: (1) a circuit for deriving a carry out bit from a carry in bit and first and second addend and augend bits that includes first, second and third threshold logic gates that generate intermediate bits based on threshold comparisons of concatenations of said carry in bit and said first and second addend and augend bits, and (2) combinatorial boolean logic that generates said carry out bit from said intermediate bits.

Abstract: A circuit and method for deriving an adder output bit from adder input bits, a multiplier circuit, a method of multiplying, a microprocessor and digital signal processor (DSP) employing the circuit or the method and a method of selecting weights and thresholds for logic gates. In one embodiment, the circuit includes: (1) first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of ones of the adder input bits and (2) combinatorial logic that generates the adder output bit from the intermediate bits. In one embodiment, the multiplier includes a summer having at least two inputs with corresponding weights, the inputs corresponding to bits of a multiplicand, the weights based on a multiplier, the summer generating a weighted sum of the multiplicand that represents a multiplication of the multiplicand and the multiplier that is a function of the weighted sum.

Abstract: An adder, a processor (such as a microprocessor or digital signal processor), and methods of adding in such adder or processor. In one embodiment, the adder includes: (1) a first and second units in a first logic layer, the first unit receiving first and second addend and augend bits and generating therefrom a first single group-carry-generate bit and first and second carry-propagate bits, the second unit receiving third and fourth addend and augend bits and generating therefrom a second single group-carry-generate bit and third and fourth carry-propagate bits and (2) a third unit in a second logic layer, coupled to the first and second units, that receives the first and second single group-carry-generate bits and the first, second, third and fourth carry-propagate bits and generates therefrom resulting group-carry-generate and group-carry-propagate bits.

Abstract: A logic gate, an adder and methods of operating and manufacturing the same. In one embodiment, the logic gate includes: (1) a summer, having at least two single-bit inputs and a noise-suppression input with corresponding conductances representing discrete weights, that generates a weighted sum of input binary digits presented at the at least two single-bit inputs and the noise-suppression input and (2) a quantizer, coupled to the summer, that generates an output binary digit at a binary output thereof that is a function of the weighted sum, the noise-suppression input increasing a noise tolerance of the logic gate.

Abstract: A circuit for, and method of, decreasing DC power dissipation in a logic gate and a processor incorporating the circuit or the method. In one embodiment, wherein the logic gate has at least two binary inputs adapted to receive corresponding input binary digits, the circuit includes: (1) a combinatorial logic power down circuit that develops a power down signal as a function of an input-data signal and at least one of the input binary digits and (2) a switch, coupled to the power down circuit, that interrupts DC current to at least a portion of the logic gate as a function of the power down signal.

Abstract: A circuit and method for deriving an adder output bit from adder input bits, a multiplier circuit, a method of multiplying, a microprocessor and digital signal processor (DSP) employing the circuit or the method and a method of selecting weights and thresholds for logic gates. In one embodiment, the circuit includes: (1) first, second and third logic gates that generate intermediate bits based on threshold comparisons of concatenations of ones of the adder input bits and (2) combinatorial logic that generates the adder output bit from the intermediate bits. In one embodiment, the multiplier includes a summer having at least two inputs with corresponding weights, the inputs corresponding to bits of a multiplicand, the weights based on a multiplier, the summer generating a weighted sum of the multiplicand that represents a multiplication of the multiplicand and the multiplier that is a function of the weighted sum.