Abstract: A digital controlled oscillator (14) generates an oscillator clock that is phase locked to a reference clock. A control circuit (12) generates a reset signal from the reference clock that sets the edges of the oscillator signal in line with an edge of the reference clock. The reset signal must have correct timing and duration. A course tune detector (16, 18) monitors the oscillator clock and generates course tune control signals (CT) that adjust the reset signal pulse width and the oscillator signal frequency by adding and removing capacitors from the inverters in the control circuit and digital controlled oscillator. A phase comparator (22) compares the reference clock and the oscillator clock. A fine tune detector (20) monitors the phase comparison and generates fine tune control signals (FT) that make fine adjustments to the pulse width of the reset signal and the frequency of the oscillator signal.