Abstract: The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality of NAND strings, and each NAND string includes memory cells and at least a string selection transistor. The common word lines are configured above the semiconductor layers, wherein each common word line is coupled to the memory cells arranged in a same row of the semiconductor layers. The common bit lines are configured on the common word lines, wherein each common bit line is coupled to a first ends of the NAND strings arranged in the same column of the semiconductor layers. The common source line is configured on the common word lines and coupled to a second ends of the NAND strings of the semiconductor layers.

Abstract: The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality of NAND strings, and each NAND string includes memory cells and at least a string selection transistor. The common word lines are configured above the semiconductor layers, wherein each common word line is coupled to the memory cells arranged in a same row of the semiconductor layers. The common bit lines are configured on the common word lines, wherein each common bit line is coupled to a first ends of the NAND strings arranged in the same column of the semiconductor layers. The common source line is configured on the common word lines and coupled to a second ends of the NAND strings of the semiconductor layers.

Abstract: A data programming method and a system thereof are provided to program an original data into a memory. In the method, the original data complying with a first data arrangement rule is converted into an intermediate data complying with a second data arrangement rule, wherein the second arrangement rule corresponds to a type of the memory. Next, the intermediate data is analyzed to obtain at least one failure area which causes program disturb, and the content of the at least one failure area is replaced by a corresponding adjustment code. The replaced intermediate data is encoded, and a corresponding encoding information is generated. After the encoded intermediate data and the encoding information are both converted into a non-failure data complying with the first data arrangement rule, the non-failure data is programmed into the memory.