Abstract: The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality of NAND strings, and each NAND string includes memory cells and at least a string selection transistor. The common word lines are configured above the semiconductor layers, wherein each common word line is coupled to the memory cells arranged in a same row of the semiconductor layers. The common bit lines are configured on the common word lines, wherein each common bit line is coupled to a first ends of the NAND strings arranged in the same column of the semiconductor layers. The common source line is configured on the common word lines and coupled to a second ends of the NAND strings of the semiconductor layers.

Abstract: The invention provides a memory device on a substrate. The memory device comprises semiconductor layers, common word lines, common bit lines and a common source line. The semiconductor layers are stacked on the substrate, wherein each semiconductor layer has a plurality of NAND strings, and each NAND string includes memory cells and at least a string selection transistor. The common word lines are configured above the semiconductor layers, wherein each common word line is coupled to the memory cells arranged in a same row of the semiconductor layers. The common bit lines are configured on the common word lines, wherein each common bit line is coupled to a first ends of the NAND strings arranged in the same column of the semiconductor layers. The common source line is configured on the common word lines and coupled to a second ends of the NAND strings of the semiconductor layers.