Patents Assigned to ROCKETICK TECHNOLOGIES LTD.
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Patent number: 10509876Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs—108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.Type: GrantFiled: June 3, 2015Date of Patent: December 17, 2019Assignee: Rocketick Technologies LTDInventors: Uri Tal, Shay Mizrachi, Tomer Ben-David
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Patent number: 9684494Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.Type: GrantFiled: March 16, 2015Date of Patent: June 20, 2017Assignee: ROCKETICK TECHNOLOGIES LTD.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher, Ronen Gal
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Patent number: 9684744Abstract: A method for design verification includes receiving a definition of a design of an integrated circuit device and at least one assertion of a property that is to be verified over the design. The definition is compiled into a graph of processing elements, including first processing elements that simulate operation of the device and at least one second processing element representing the at least one assertion. The at least one second processing element includes a hierarchical arrangement of at least one operator node and one or more leaf nodes corresponding to inputs of the at least one assertion. A simulation of the design is executed by triggering the processing elements in the graph in multiple, consecutive clock cycles and evaluating the property during execution of the simulation.Type: GrantFiled: October 15, 2015Date of Patent: June 20, 2017Assignee: Rocketick Technologies LTD.Inventors: Ishay Geller, Guy Rom, Shay Mizrachi
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Patent number: 9672065Abstract: A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.Type: GrantFiled: July 26, 2015Date of Patent: June 6, 2017Assignee: Rocketick Technologies LTDInventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher
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Patent number: 9128748Abstract: A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.Type: GrantFiled: April 12, 2011Date of Patent: September 8, 2015Assignee: ROCKETICK TECHNOLOGIES LTD.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher
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Patent number: 9087166Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.Type: GrantFiled: April 28, 2014Date of Patent: July 21, 2015Assignee: ROCKETICK TECHNOLOGIES LTD.Inventors: Uri Tal, Shay Mizrachi, Tomer Ben-David
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Patent number: 9032377Abstract: A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.Type: GrantFiled: June 2, 2013Date of Patent: May 12, 2015Assignee: Rocketick Technologies Ltd.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher, Ronen Gal
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Publication number: 20140379320Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.Type: ApplicationFiled: April 28, 2014Publication date: December 25, 2014Applicant: ROCKETICK TECHNOLOGIES LTD.Inventors: Uri Tal, Shay Mizrachi, Tomer Ben-David
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Patent number: 8751211Abstract: A method for design simulation includes partitioning a verification task of a design into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device, which includes a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.Type: GrantFiled: March 25, 2009Date of Patent: June 10, 2014Assignee: Rocketick Technologies Ltd.Inventors: Uri Tal, Shay Mizrachi, Tomer Ben-David
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Patent number: 8516454Abstract: A computing method includes accepting a definition of a computing task (68), which includes multiple atomic Processing Elements (PEs—76) having execution dependencies (80). Each execution dependency specifies that a respective first PE is to be executed before a respective second PE. The computing task is compiled for concurrent execution on a multiprocessor device (32), which includes multiple processors (44) that are capable of executing a first number of the PEs simultaneously, by arranging the PEs, without violating the execution dependencies, in an invocation data structure (90) including a second number of execution sequences (98) that is greater than one but does not exceed the first number. The multiprocessor device is invoked to run software code that executes the execution sequences in parallel responsively to the invocation data structure, so as to produce a result of the computing task.Type: GrantFiled: June 30, 2009Date of Patent: August 20, 2013Assignee: Rocketick Technologies Ltd.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David
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Publication number: 20110191092Abstract: A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.Type: ApplicationFiled: April 12, 2011Publication date: August 4, 2011Applicant: ROCKETICK TECHNOLOGIES LTD.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David, Ishay Geller, Ido Kasher
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Publication number: 20110067016Abstract: A computing method includes accepting a definition of a computing task (68), which includes multiple atomic Processing Elements (PEs—76) having execution dependencies (80). Each execution dependency specifies that a respective first PE is to be executed before a respective second PE. The computing task is compiled for concurrent execution on a multiprocessor device (32), which includes multiple processors (44) that are capable of executing a first number of the PEs simultaneously, by arranging the PEs, without violating the execution dependencies, in an invocation data structure (90) including a second number of execution sequences (98) that is greater than one but does not exceed the first number. The multiprocessor device is invoked to run software code that executes the execution sequences in parallel responsively to the invocation data structure, so as to produce a result of the computing task.Type: ApplicationFiled: June 30, 2009Publication date: March 17, 2011Applicant: ROCKETICK TECHNOLOGIES LTD.Inventors: Shay Mizrachi, Uri Tal, Tomer Ben-David
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Publication number: 20100274549Abstract: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.Type: ApplicationFiled: March 25, 2009Publication date: October 28, 2010Applicant: ROCKETICK TECHNOLOGIES LTD.Inventors: Uri Tal, Shay Mizrachi, Tomer Ben-David