Abstract: An image generating apparatus for generating an output image based on an input panorama image, includes a parameter input unit inputting an output range parameter and a correction parameter, the output range parameter designating an output range in the panorama image, the correction parameter designating a correction part to be corrected in the output image; and an image correction unit correcting the correction part designated by the correction parameter in the output image. Further, the image correction unit calculates a similarity between the correction part and peripheral pixels and corrects the correction part based on the similarity and the peripheral pixels, and the output image is generated from the output range of the panorama image and is the panorama image corrected by the correction.

Abstract: A carrier comprising a magnetic core particle having a shape factor SF-2 of 130 to 160 and a resin layer covering a surface of the magnetic core particle. The resin layer comprises a conductive particle and a resin obtained by heating a copolymer comprising a silicon-containing A unit and another silicon-containing B unit.

Abstract: A memory precharge voltage, VPC, is provided which tracks changes in the high voltage supply, VDD, according to a measured degree, which maintains a precharge voltage notwithstanding transient loads which may tend to draw the precharge voltage down, and which maintains the precharge voltage at the operating level notwithstanding the fact that the precharge generator is substantially turned off during a power down condition. The precharge voltage, VPC, is then used as the controlling input signal to a circuit which it generates and an internal control voltage, MLC, used to drive small pull-up current FETs coupled to the bit lines in the ROM core. The internal control signal MLC is generated to track the discharge current in a bit line within the memory core, to track VPC, and to be maintained at its operating voltage level even when the MLC current is substantially turned off during a power down condition.

Abstract: The invention is a control circuit for controlling an interrupt driver coupled to the data outputs of a memory having address transition detection circuitry. The memory is operable in a standby and an active memory mode in sequential memory cycles. The control circuit comprises an output enable latch circuit which provides internal memory signal of whether the memory was operating in the standby or active mode during a previous memory cycle and a data latch circuit which provides an internal memory signal of whether a new read cycle is beginning within the memory. The data latch circuit is reset when address detection has occurred within the memory. A logic circuit combines an output of the data latch circuit, which is indicative of a memory read cycle, with an output of the output enable latch circuit, which is indicative of whether the prior memory cycle was standby or active.

Abstract: The invention is a dynamic ROM design for read cycle interrupts. The clock scheme of the improved memory generates a primary start clock. The relatively long pulse time of START when high is provided for setting the latches. This pulse duration is controlled by PCOK or OWDN one shot circuit.When an address interrupt occurs early in the read cycle, while PCOK or OWDN clock is low, and START is high, these one shot circuits provide a simple means of restarting the cycle by continuing the precharge phase of the cycle with no effect on most of the secondary clocks in the memory. Only those clocks relating to the new address inputs are effected by the early interrupt. This results in less power dissipation and less bus noise.

Abstract: A copier selectively operable in a cover plate mode which uses a cover plate and an automatic document feeder (ADF) mode which uses an ADF. After a cover plate mode operation of the copier, a person is inhibited from operating the copier when a condition wherein the cover plate is closed and documents are loaded on a document feed table of the copier is detected.

Abstract: An image signal processing method in which an image light is projected on photoelectric conversion means and an image signal produced by said photoelectric conversion means is changed into an image signal in a binary form. The amplitude and level of an information signal to be binarily processed are kept nearly constant according to the invention and consequently the binary processing can be performed with a least leakage of informations.