Abstract: A porous polishing pad is useful for polishing semiconductor substrates. The porous polishing pad has a porous matrix formed from a coagulated polyurethane and a non-fibrous polishing layer. The non-fibrous polishing layer has a polishing surface with a pore count of at least 500 pores per mm2 that decreases with removal of the polishing layer; and the polishing surface has a surface roughness Ra between 0.01 and 3 ?m.
Type:
Grant
Filed:
July 30, 2003
Date of Patent:
May 31, 2005
Assignee:
Rohm and Haas Electronic Materials CMP Holdings, NC
Inventors:
Clyde A. Fawcett, T. Todd Crkvenac, Kenneth A. Prygon, Bernard Foster