Abstract: A power supply device includes an output transistor provided in series between an input terminal via which to receive an input voltage and an output terminal via which to deliver an output voltage, and is configured to generate the output voltage by bucking the input voltage through control of the state of the output transistor. The power supply device includes a short circuit protection circuit configured to perform short circuit protection operation by keeping off the output transistor based on the output voltage, and a masking circuit configured to be able to mask the short circuit protection operation based on the input voltage and the output voltage.

Abstract: A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.

Abstract: An intelligent power module includes: a heat radiation device; an attachment frame disposed on a mounting surface of the heat radiation device; a power semiconductor module mounted on the attachment frame and configured to seal a semiconductor device; and a drive circuit part mounted on the power semiconductor module via a heat insulating sheet and configured to drive the power semiconductor module.

Abstract: A semiconductor device includes a SiC semiconductor layer that has a carbon density of 1.0×1022 cm?3 or more, a SiO2 layer that is formed on the SiC semiconductor layer and that has a connection surface contiguous to the SiC semiconductor layer and a non-connection surface positioned on a side opposite to the connection surface, a carbon-density-decreasing region that is formed at a surface layer portion of the connection surface of the SiO2 layer and in which a carbon density gradually decreases toward the non-connection surface of the SiO2 layer, and a low carbon density region that is formed at a surface layer portion of the non-connection surface of the SiO2 layer and that has a carbon density of 1.0×1019 cm?3 or less.

Abstract: A communication system is configured to use a pulse width modulation signal as transmission code among a plurality of nodes connected to a communication line. A master node includes a transmission transistor connected to the communication line, a detector configured to detect a variation in current during the on-period of the transmission transistor, and a communication circuit configured to determine the off-timing of the transmission transistor based on the timing of occurrence of the variation in current (i.e., the on-timing of a second transmission transistor provided in a slave node). For example, the communication circuit can be configured to determine the off-timing of the transmission transistor such that the simultaneously-on period TB of the transmission transistor and the second transmission transistor fulfills TB=(2n?1)/2f, where f is the frequency of EMI noise.

Abstract: A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.

Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

Abstract: The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

Abstract: A semiconductor device includes: a substrate with an obverse surface facing in a thickness direction; first and second wirings on the obverse surface; and a semiconductor element with a first electrode facing the obverse surface and an adjacent second electrode facing the obverse surface. The first electrode is electrically bonded to the first wiring, and the second electrode bonded to the second wiring. The substrate includes first, second and third sections, with the first section including a portion of the obverse surface and overlapping with the first wiring and first electrode as viewed in the thickness direction. The second section includes a portion of the obverse surface, overlapping with the second wiring and second electrode as viewed in the thickness direction. The third section, located between the first and the second sections as viewed in the thickness direction, includes a first surface with its normal direction intersecting the thickness direction.

Abstract: A chip inductor includes a sealing body having a mounting surface and a coil conductor sealed in an interior of the sealing body, wherein the coil conductor includes a first coil end exposed from the mounting surface of the sealing body, a second coil end exposed from the mounting surface of the sealing body, and a spiral portion of spiral form connected to the first coil end and the second coil end and routed along a normal direction of the mounting surface of the sealing body from the first coil end and the second coil end.

Abstract: A semiconductor device includes: a semiconductor element that includes an element main body having an element main surface facing one side in a thickness direction, and a first electrode arranged on the element main surface; a first insulating layer that is arranged over a peripheral edge portion of the first electrode and the element main surface and includes a first annular portion formed in an annular shape when viewed in the thickness direction; and a second insulating layer that is laminated on the first insulating layer, is made of a resin material, and includes a second annular portion overlapping with the first annular portion when viewed in the thickness direction.

Abstract: A semiconductor device includes a conductive member including first, second and third conductors mutually spaced, a first semiconductor element having a first obverse surface provided with a first drain electrode, a first source electrode and a first gate electrode, and a second semiconductor element having a second obverse surface provided with a second drain electrode, a second source electrode and a second gate electrode. The first conductor is electrically connected to the first source electrode and the second drain electrode. The second conductor is electrically connected to the second source electrode. As viewed in a first direction crossing the first obverse surface, the second conductor is adjacent to the first conductor in a second direction crossing the first direction. The third conductor is electrically connected to the first drain electrode and is adjacent to the first conductor and the second conductor as viewed in the first direction.

Abstract: A semiconductor device includes a substrate including a main surface, a semiconductor element mounted on the main surface, a drive pad, and drive wires. The semiconductor element includes a front surface that faces in a same direction as the main surface and a drive electrode formed on the front surface and containing SiC. The drive wires are spaced apart from each other and connect the drive electrode to the drive pad. The drive wires include a first drive wire and a second drive wire configured to be a combination of furthermost ones of the drive wires. The first drive wire and the second drive wire are separated from each other by a greater distance at the drive pad than at the drive electrode as viewed in a first direction that is perpendicular to the main surface of the substrate.

Abstract: An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.

Abstract: A semiconductor device includes: a first semiconductor layer of a first conductivity type; at least one second semiconductor layer of a second conductivity type formed in the first semiconductor layer to have an annular shape in plan view; an insulating layer formed on the first semiconductor layer; a first metal layer and a second metal layer formed on the insulating layer and spaced apart from each other; a second wiring layer provided in the insulating layer and configured to electrically connect an inner region of the first semiconductor layer surrounded by the at least one second semiconductor layer and the second metal layer; and a first wiring layer provided in the insulating layer and configured to electrically connect an outer region of the first semiconductor layer on the opposite side from the inner region with respect to the at least one second semiconductor layer and the first metal layer.

Abstract: This nitride semiconductor device is provided with: a depletion type transistor which comprises a first gate terminal, a first source terminal and a first drain terminal; and an enhancement type transistor which comprises a second gate terminal, a second source terminal and a second drain terminal. The second drain terminal is connected to the first source terminal; and the second source terminal is connected to the first gate terminal. The depletion type transistor comprises: an electron transit layer which is configured from a nitride semiconductor that contains aluminum in the crystal composition; and an electron supply layer which is formed on the electron transit layer and is configured from a nitride semiconductor that contains a larger amount of aluminum in the composition than the electron transit layer.

Abstract: A nitride semiconductor device 1 includes a conductive SiC substrate 2 that has a first surface 2a and a second surface 2b opposite thereto, a semi-insulating SiC layer 3 that is formed in at least a portion of a surface layer portion at the first surface 2a side of the conductive SiC substrate 2, and a nitride epitaxial layer 40 that is formed on the conductive SiC substrate 2 such as to cover the semi-insulating SiC layer 3.

Abstract: A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side, a plurality of gate electrodes that are arranged at intervals on the first main surface of the semiconductor layer, an interlayer insulating film that is formed on the first main surface of the semiconductor layer such as to cover the gate electrodes, an electrode film that is formed on the interlayer insulating film, and a plurality of tungsten plugs that, between a pair of the gate electrodes that are mutually adjacent, are respectively embedded in a plurality of contact openings formed in the interlayer insulating film at intervals in a direction in which the pair of mutually adjacent gate electrodes face each other and each have a bottom portion contacting the semiconductor layer and a top portion contacting the electrode film.

Abstract: A semiconductor device 1 includes a base body 3 that includes a p type substrate 4 and an n type semiconductor layer 5 formed on the p type substrate 4 and includes an element region 2 having a transistor 40 with the n type semiconductor layer as a drain, a p type element isolation region 7 that is formed in a surface layer portion of the base body such as to demarcate the element region, and a conductive wiring 25 that is disposed on a peripheral edge portion of the element region and is electrically connected to the n type semiconductor layer. The transistor includes an n+ type drain contact region 14 that is formed in a surface layer portion of the n type semiconductor layer in the peripheral edge portion of the element region. The conductive wiring is disposed such as to cover at least a portion of an element termination region 30 between the n+ type drain contact region and the p type element isolation region.

Abstract: A semiconductor device includes: a semiconductor layer having a surface; a first region and a second region of a first conductivity type, which are spaced apart from each other in a first direction on the surface and extend in a second direction orthogonal to the first direction, when viewed from a thickness direction orthogonal to the surface; a channel region of a second conductivity type; a gate electrode arranged on the channel region via a gate insulating film; a plurality of drift regions of a first conductivity type and a plurality of column regions of the second conductivity type; a buffer region of the first conductivity type; and at least one collector region of the second conductivity type.