Abstract: In a logic integrated circuit such as an FPGA, a controller reads in an instruction, and then directly transmits ON/OFF information for each of bits composing microcode included in the instruction, to registers and data memories that are allocated to each of the bits through control lines, to thereby control the registers and data memories. Thus, processing executed by the controller is simplified in this construction. This allows makings the controller having a simple structure, thereby making it possible to construct a simple CPU core on the logic integrated circuit such as the FPGA, decreasing a space of analytic logic, and eliminating necessity for re-integrating a hardware circuit every time the logic is renewed.

Abstract: In an integrated circuit, an FPGA (2) has functions of a CPU core (5), and includes a user's circuit and so forth. This configuration allows the number of implemented components such as peripheral circuit chips to be decreased, and cost to be reduced. The integrated circuit is configured such that the CPU core (5), peripheral circuits thereof, and a system bus (8) are stored as logic data in a PROM (3), and the FPGA (2) performs functions as the CPU core (5), peripheral circuits (6) (7), and system bus (8) based on the logic data. Therefore, the CPU core (5), peripheral circuits (6) (7), and system bus (8) which have desired functions can be obtained according to contents of the logic data stored in the PROM (3). Further, a user can readily extend and change functions of the CPU core (5) by retrofitting a separate circuit to the system bus (8).

Abstract: In a logic integrated circuit such as an FPGA, a controller reads in an instruction, and then directly transmits ON/OFF information for each of bits composing microcode included in the instruction, to registers and data memories that are allocated to each of the bits through control lines, to thereby control the registers and data memories. Thus, processing executed by the controller is simplified in this construction. This allows makings the controller having a simple structure, thereby making it possible to construct a simple CPU core on the logic integrated circuit such as the FPGA, decreasing a space of analytic logic, and eliminating necessity for re-integrating a hardware circuit every time the logic is renewed.

Abstract: In a CPU core development support system for an FPGA or the like, if a user defines information about addition, change and deletion of instructions of assembly language from a customizing screen, an assembler generating compiler generates a source program of an assembler which takes in a new grammatical rule in response to the addition, change and deletion of the instructions into a basic grammatical rule of the assembly language based on the information about addition, change or deletion of the instructions, and the basic grammatical rule of the assembly language. This makes it easier to add, change and delete the instructions of the assembly language, thereby allowing constructing a convenient CPU core in response to specifications of other IPs.