Patents Assigned to Round Rock Research
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Patent number: 9390004Abstract: Methods and apparatus for managing data storage in hybrid memory devices utilizing single level and multi-level memory cells. Logical addresses can be distributed between single level and multilevel memory cells based on a frequency of write operations performed. Initial storage of data corresponding to a logical address in memory can be determined by various methods including initially writing all data to single level memory or initially writing all data to multilevel memory. Other methods permit a host to direct logical address writes to single level or multilevel memory cells based on anticipated usage.Type: GrantFiled: May 30, 2014Date of Patent: July 12, 2016Assignee: Round Rock Research, LLCInventors: William Radke, Michael Murray, Martin Ragnar Furuhjelm, John Geldman
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Patent number: 9348722Abstract: A network of microcontrollers for monitoring and diagnosing the environmental conditions of a computer is disclosed. The network of microcontrollers provides a management system by which computer users can accurately gauge the health of their computer. The network of microcontrollers provides users the ability to detect system fan speeds, internal temperatures and voltage levels. The invention is designed to not only be resilient to faults, but also allows for the system maintenance, modification, and growth—without downtime. Additionally, the present invention allows users to replace failed components, and add new functionality, such as new network interfaces, disk interface cards and storage, without impacting existing users. One of the primary roles of the present invention is to manage the environment without outside involvement. This self-management allows the system to continue to operate even though components have failed.Type: GrantFiled: October 21, 2013Date of Patent: May 24, 2016Assignee: Round Rock Research, LLCInventors: Karl S. Johnson, Walter A. Wallach, Ken Nguyen, Carlton G. Amdahl
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Patent number: 9235526Abstract: A non-volatile hard disk drive cache system is coupled between a processor and a hard disk drive. The cache system includes a control circuit, a non-volatile memory and a volatile memory. the control circuit causes a subset of the data stored in the hard disk drive to be written to the non-volatile memory. In response to a request to read data are stored in the non-volatile memory. If so, the requested read data are provided form the non-volatile memory. Otherwise, the requested read data are provided from the hard disk drive. the volatile memory is used as a write buffer and to store disk access statistics, such as the disk drive locations that are most frequently read, which are used by the control circuit to determine which data to store in the non-volatile memory.Type: GrantFiled: September 12, 2014Date of Patent: January 12, 2016Assignee: Round Rock Research, LLCInventor: Dean A. Klein
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Patent number: 9201730Abstract: A system having a non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Blocks can operate in either a multiple bit per cell mode or a single bit per cell mode. A processor controls the system and selects blocks to operate in the multiple bit per cell mode and single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode.Type: GrantFiled: December 24, 2013Date of Patent: December 1, 2015Assignee: Round Rock Research, LLCInventor: Frankie F. Roohparvar
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Patent number: 9196368Abstract: Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.Type: GrantFiled: January 20, 2014Date of Patent: November 24, 2015Assignee: Round Rock Research, LLCInventors: Giulio Marotta, Luca De Santis, Tommaso Vali
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Patent number: 9159427Abstract: Systems comprising an array of memory cells organized into a plurality of erasable physical blocks, the address of physical block associated with an array of memory cells having a predetermined logical erase block size, wherein at least of the logical erase block size is smaller than another logical erase block size and a processor that selects the storage of data among different logical erase blocks in the array of memory cells based upon programmable and predetermined criteria.Type: GrantFiled: December 2, 2013Date of Patent: October 13, 2015Assignee: Round Rock Research, LLCInventor: Frankie F. Roohparvar
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Patent number: 9142263Abstract: A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by logically ORing, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation.Type: GrantFiled: December 24, 2013Date of Patent: September 22, 2015Assignee: Round Rock Research, LLCInventor: Dean A. Klein
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Patent number: 9117095Abstract: A computing system includes data encryption in the data path between a data source and data storage devices. The data encryption may utilize a key which is derived at least in part from an identification code stored in a nonvolatile memory. The key may also be derived at least in part from user input to the computer.Type: GrantFiled: September 9, 2013Date of Patent: August 25, 2015Assignee: Round Rock Research LLCInventor: Dean A Klein
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Patent number: 9082461Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.Type: GrantFiled: August 7, 2012Date of Patent: July 14, 2015Assignee: Round Rock Research, LLCInventor: Joseph M. Jeddeloh
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Patent number: 9015553Abstract: The present disclosure includes methods, devices, and systems for data integrity in memory controllers. One memory controller embodiment includes a host interface and first error detection circuitry coupled to the host interface. The memory controller can include a memory interface and second error detection circuitry coupled to the memory interface. The first error detection circuitry can be configured to calculate error detection data for data received from the host interface and to check the integrity of data transmitted to the host interface. The second error detection circuitry can be configured to calculate error correction data for data and first error correction data transmitted to the memory interface and to check integrity of data and first error correction data received from the memory interface.Type: GrantFiled: June 18, 2013Date of Patent: April 21, 2015Assignee: Round Rock Research, LLCInventors: Mehdi Asnaashari, Ronald Yamada, Siamack Nemazie, Jui-Yao Yang
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Patent number: 9014077Abstract: A method of establishing wireless communications between an interrogator and individual ones of multiple wireless identification devices, the method comprising combining tree search and Aloha methods to establish communications between the interrogator and individual ones of the multiple wireless identification devices without collision. A system comprising an interrogator, and a plurality of wireless identification devices configured to communicate with the interrogator In a wireless fashion, the respective wireless identification devices having a unique identification number, the interrogator being configured to employ tree search and Aloha techniques to determine the unique identification numbers of the different wireless identification devices so as to be able to establish communications between the interrogator identification and individual devices without ones of the multiple wireless collision by multiple wireless identification devices attempting to respond to the interrogator at the same time.Type: GrantFiled: January 27, 2014Date of Patent: April 21, 2015Assignee: Round Rock Research, LLCInventor: Clifton W. Wood, Jr.
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Patent number: 8994505Abstract: Methods and apparatuses to secure data transmission in a radio frequency identification (RFID) system against eavesdropping, using multiple communication channels. In one embodiment, a method includes communicating key information and cipher text generated based on the key information, or plain text, using a plurality of different, distinct and separate communication channels connected to an RFID tag.Type: GrantFiled: October 17, 2013Date of Patent: March 31, 2015Assignee: Round Rock Research, LLCInventor: John R. Tuttle
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Patent number: 8981444Abstract: Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.Type: GrantFiled: November 22, 2011Date of Patent: March 17, 2015Assignee: Round Rock Research, LLCInventors: Kevin J. Torek, Mark Fischer, Robert J. Hanson
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Patent number: 8935505Abstract: A system with a processor in communication with a memory controller in communication with a plurality of memory devices wherein one of the plurality of memory devices is interposed between the memory controller and the remaining plurality of memory devices. By programming command delay in the memory controller, the command delay coordinates the execution of the command signal across all memory devices. The processor provides control signals to the memory controller that, in response, decodes the control signals and determines the mode of operation of one or more of the memory devices. The processor is also in communication with storage media and stores data in or retrieves data from the storage media.Type: GrantFiled: December 2, 2013Date of Patent: January 13, 2015Assignee: Round Rock Research, LLCInventor: Douglas Alan Larson
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Publication number: 20140361753Abstract: A temperature sensing device can be embedded in a memory module or system in order to sense the temperature of the memory module or system. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature.Type: ApplicationFiled: August 22, 2014Publication date: December 11, 2014Applicant: Round Rock Research, LLCInventor: Simon J. Lovett
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Patent number: 8908453Abstract: Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided.Type: GrantFiled: October 16, 2013Date of Patent: December 9, 2014Assignee: Round Rock Research, LLCInventor: Thomas H. Kinsley
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Patent number: 8896730Abstract: An imager has first and second photosensitive sites and an interpolator located in a semiconductor substrate. The first photosensitive site is configured to receive light having a spectral component, and the second photosensitive site is configured to measure the level of the spectral component in light received by the second photosensitive site. The interpolator is configured to estimate the level of the spectral component in the light received by the first photosensitive site based on the measurement by the second photosensitive site.Type: GrantFiled: December 20, 2013Date of Patent: November 25, 2014Assignee: Round Rock Research, LLCInventor: Eric R. Fossum
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Patent number: RE45282Abstract: An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available. A system includes a CMOS active pixel image sensor having an array for photoreceptors to convert an image into an analog signal. The CMOS image sensor converts the analog signal into a digital signal using a pipelined analog to digital converter.Type: GrantFiled: January 24, 2012Date of Patent: December 9, 2014Assignee: Round Rock Research, LLCInventors: Eric R. Fossum, Sandor L. Barna
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Patent number: RE45357Abstract: A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in the doped area. The invention also provides a CMOS imager where a photodetector sensor array is formed in a first p-well and readout logic is formed in a second p-well. The first p-well can be selectively doped to optimize cross-talk, collection efficiency and transistor leakage, thereby improving the quantum efficiency of the sensor array while the second p-well can be selectively doped and/or biased to improve the speed and drive of the readout circuitry.Type: GrantFiled: February 26, 2010Date of Patent: February 3, 2015Assignee: Round Rock Research, LLCInventor: Howard E. Rhodes
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Patent number: RE45493Abstract: An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available. A CMOS image sensor converts successive analog signals, representing at least a portion of an image, into successive digital signals using an analog to digital circuit block. Multiple clock cycles may be used by the circuit block to fully convert an analog signal into a corresponding digital signal. The conversion of one analog signal into a corresponding digital signal by the circuit block may be offset in time and partially overlapping with the conversion of a successive analog signal into its corresponding successive digital signal by the circuit block.Type: GrantFiled: June 25, 2012Date of Patent: April 28, 2015Assignee: Round Rock Research, LLCInventors: Eric R. Fossum, Sandor L. Barna