Abstract: An integrated controller for motion control and motor control comprises a first processor, a second processor, a cache and a shared memory. The first processor is configured to run an operating system and at least perform motion control. The second processor is configured to at least perform motor control and normally not run the operating system. The cache is coupled to the first processor and the second processor. The shared memory maps onto the cache. The first processor and the second processor are configured to share the shared memory and accordingly perform data transmission via the cache during the periods of motion control and motor control. The first processor, the second processor and the cache are integrated in a same chip.