Patents Assigned to Ryoden Semiconductor System Engineering
  • Patent number: 6458655
    Abstract: A semiconductor manufacturing method is mainly contemplated, improved to prevent an altered surface layer of a resist from being removed when a single patterned resist is used to provide dry-etch and wet-etch successively. On a semiconductor substrate an insulation film and a conductive layer are formed successively. On the conductive layer a patterned resist is formed. With the patterned resist used as a mask, the conductive layer is dry-etched. A surface layer of the patterned resist is partially removed. With the patterned resist used as a mask, the insulation film is wet-etched.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: October 1, 2002
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Ryoden Semiconductor System Engineering
    Inventors: Kojiro Yuzuriha, Shu Shimizu, Tamotsu Tanaka, Takashi Yano