Abstract: Embodiments of the present disclosure provide methods, apparatuses, and systems including a memory device including content addressable memory configured to store an address associated with one or more memory cells while an access operation is performed on the one or more memory cells. Other embodiments may be described.

Abstract: Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may be part of a data word comprising a plurality of bits and both the determining and the writing may be performed at a granularity level finer than a data word. In embodiments, the bit to be written may be determined by error correction.

Abstract: Random access memory with CMOS-compatible nonvolatile storage element in series with storage capacitor is described herein. Embodiments may include memory devices and systems that have plurality of row lines, column lines, and memory cells each of which comprising an access transistor, a storage capacitor and a CMOS-compatible non-volatile storage element connected in series. The CMOS-compatible non-volatile storage element may store charges corresponding to a binary value. The node located between the CMOS-compatible non-volatile storage element and the storage capacitor may be defined as a storage node. During read operation, a cell may be selected, and the voltage at the storage node of the cell may be sensed at the corresponding column line, and the binary value may be determined based on at least the sensed voltage.

Abstract: Methods and apparatus for controlling an input/output (I/O) driver of an I/O terminal based at least in part on the values being provided to the I/O terminal is disclosed. In various embodiments, a detector is employed. The detector shuts off power to the I/O driver if the digital value being presented is the same as a previously presented digital value.

Abstract: Random access memory with CMOS-compatible nonvolatile storage element in series with storage capacitor is described herein. Embodiments may include memory devices and systems that have plurality of row lines, column lines, and memory cells each of which comprising an access transistor, a storage capacitor and a CMOS-compatible non-volatile storage element connected in series. The CMOS-compatible non-volatile storage element may store charges corresponding to a binary value. The node located between the CMOS-compatible non-volatile storage element and the storage capacitor may be defined as a storage node. During read operation, a cell may be selected, and the voltage at the storage node of the cell may be sensed at the corresponding column line, and the binary value may be determined based on at least the sensed voltage.

Abstract: Embodiments of the present disclosure provide methods, apparatuses, and systems including a memory device including content addressable memory configured to store an address associated with one or more memory cells while an access operation is performed on the one or more memory cells. Other embodiments may be described.

Abstract: Embodiments of the present disclosure provide methods, apparatuses, and systems including a memory arrangement including a first memory, and a second memory operatively coupled to the first memory to serve as an external interface of the memory arrangement to one or more components external to the memory arrangement to access different portions of the first memory concurrently. Other embodiments may be described.

Abstract: Embodiments of the present disclosure provide methods, apparatuses and systems including a storage configured to store and output multiple address strides of varying sizes to enable access and precharge circuitry to access and precharge a first and a second group of memory cells based at least in part on the multiple address strides during operation of the host apparatus/system, the first and second group of memory cells being different groups of memory cells.

Abstract: The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.