Patents Assigned to S.O.I.Tec Silicon on Insulator Technolgies
  • Patent number: 7632739
    Abstract: A process for fabricating a hybrid substrate that has a defect trapping zone. The process includes the steps of forming or depositing a first insulator layer on a first substrate of semiconductor material; increasing roughness of the first insulator layer surface; depositing a second insulator layer on the roughened surface of the first insulator to form a trapping zone between the layers; bonding a second substrate onto the second insulator layer by molecular adhesion; and transferring an active layer formed by the implantation of atomic species into one of the substrates. The trapping zone is able to retain gaseous species present at the various interfaces of the hybrid substrate to limit the formation of defects on the surface of the active layer that is transferred.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: December 15, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technolgies
    Inventor: Xavier Hebras