Patents Assigned to S.O.I. TEC Silicon On Insulator Technologies of Chemin des Franques
  • Patent number: 8329048
    Abstract: A method for trimming a structure obtained by bonding a first wafer to a second waver on contact faces and thinning the first waver, wherein at least either the first wafer or the second wafer is chamfered and thus exposes the edge of the contact face of the first wafer, wherein the trimming concerns the first wafer. The method includes a) selecting the second wafer from among wafers with a resistance to a chemical etching planned in b) that is sufficient with respect to the first wafer to allow b) to be carried out; b) after bonding the first wafer to the second wafer, chemical etching the edge of the first wafer to form in the first wafer a pedestal resting entirely on the contact face of the second wafer and supporting the remaining of the first wafer; and c) thinning the first wafer until the pedestal is reached and attacked, to provide a thinned part of the first wafer.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: December 11, 2012
    Assignees: Commissariat a l'Energie Atomique, S.O.I. TEC Silicon On Insulator Technologies of Chemin des Franques
    Inventors: Marc Zussy, Bernard Aspar, Chrystelle Lagahe-Blanchard, Hubert Moriceau