Abstract: A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions.

Abstract: A plurality of FPGAs and off-chip storage devices provide a verification module for functionally debugging electronic circuit designs. Signal value compression circuits embedded in each FPGA conserve the limited number of pins available on each FPGA. Transmitting addresses to signal values previously stored in off-chip storage further reduce the bottlenecks in analyzing logic functionality distributed across multiple FPGAs.

Abstract: A plurality of FPGAs and off-chip storage devices provide a verification module for functionally debugging electronic circuit designs. Signal value compression circuits embedded in each FPGA conserve the limited number of pins available on each FPGA. Transmitting addresses to signal values previously stored in off-chip storage further reduce the bottlenecks in analyzing logic functionality distributed across multiple FPGAs.

Abstract: A apparatus and a system and method to operate the above provide a reconfigurable platform for emulating and debugging a user design which exceeds the capacity of a single field programmable logic device (FPGA). The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with logic value tunneling circuits in an emulation using a platform including a number of field programmable devices. A verification module apparatus provides a hyper prototype for debugging an electronic design that exceeds the capacity of a single FPGA. A verification module provides access to a plurality of attached FPGAs by means of Logic Value Tunneling Transmitters and Receivers which deliver many signals over few pins.

Abstract: A apparatus and a system and method to operate the above provide a reconfigurable platform for emulating and debugging a user design which exceeds the capacity of a single field programmable logic device (FPGA). The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with logic value tunneling circuits in an emulation using a platform including a number of field programmable devices. A verification module apparatus provides a hyper prototype for debugging an electronic design that exceeds the capacity of a single FPGA. A verification module provides access to a plurality of attached FPGAs by means of Logic Value Tunneling Transmitters and Receivers which deliver many signals over few pins.

Abstract: A method and a system provide a reconfigurable platform for designing and emulating a user design. The method and system facilitates design and emulation of a system-on-a-chip type user design. The netlist of a user design may be included with netlists from customized or optimized third party circuits in an emulation using a platform including a number of field programmable devices. Various customized circuits for specific development activities, such as debugging, performance analysis, and simulator linkage may be configured to interact with the user design.