Abstract: A networking detection method and system, relating to the technical field of electronic design automation. The method specifically comprises: an upper computer (2) allocating identifier information for each system single board (1), programmable logic array (4), and signal channel, and loading the identifier information into a corresponding controller (3) (S1); uniformly setting the signal channel to a signal receiving mode (S2); detecting whether the signal channel receives a data packet (S3); and generating one interconnection data, the upper computer (2) obtaining interconnection information according to processed interconnection data, and generating a hardware system description language file for describing networking connection (S8). By means of the processing solution, manual measurement and input are not needed, no limitation is caused by a development board installation environment, the generation speed is high, the precision is high, and a faulty cable can be accurately positioned.

Abstract: A method for logic design partitioning includes: collecting an RTL design file used for describing a logic circuit; performing syntax analysis processing on the RTL design file; extracting an always object and an assign object from logic model objects, and encapsulating the always object and the assign object, respectively; constructing and generating a hypergraph-based data structure; performing attribute analysis, and obtaining operating frequency information by processing according to clock domain information; associating and storing the clock domain information and the operating frequency information with corresponding nodes; and performing partitioning processing to obtain corresponding partitioned data. By means of the solutions of the present invention, other processing at the back end of the flow is not affected, the partitioning time is reduced and the partitioning efficiency is improved. Meanwhile, the logic content in chip design is partitioned efficiently, reasonably and correctly.