Abstract: A method implemented in a graphics engine for decoding image blocks to derive an original image is provided. The method comprises receiving at least one encoded image data block at a block decoder, the at least one encoded image data block comprising a plurality of codewords and a bitmap. The method further comprises determining a block type based on the plurality of codewords and selecting a decoder unit among a plurality of decoder units in accordance with the block type.

Abstract: A method and a system for supporting multiple display adapters in the WDDM architecture are provided. A driver wrapper serves as the interface between the OS and the display drivers. The driver wrapper hides the display drivers from the knowledge of the OS and provides the standard display driver interface (DDI) to the OS. In the view of the OS, the driver wrapper is the single common driver which receives requests from the OS. The driver wrapper dispatches the requests from the OS to the display drivers and relays responses from the display drivers to the OS. The driver wrapper of the present invention is compatible with multiple distinct display drivers.

Abstract: A method implemented in a graphics engine for decoding image blocks to derive an original image is provided. The method comprises receiving at least one encoded image data block at a block decoder, the at least one encoded image data block comprising a plurality of codewords and a bitmap. The method further comprises determining a block type based on the plurality of codewords and selecting a decoder unit among a plurality of decoder units in accordance with the block type.

Abstract: An image processing system including an image encoder and image decoding system is provided. The image encoder system includes an image decomposer, a block encoder, and an encoded image composer. The image decomposer decomposes the image into blocks. The block encoder, which includes a selection module, a codeword generation module and a construction module, processes the blocks. Specifically, the selection module computes a set of parameters from image data values of a set of image elements in the image block. The codeword generation module generates codewords, which the construction module uses to derive a set of quantized image data values. The construction module then maps each of the image element's original image data values to an index to one of the derived image data values. The image decoding system reverses this process to reorder decompressed image blocks in an output data file.

Abstract: A system and method is provided which enables pixel data stored in multiple memory pages to be combined in one data packet, thereby reducing the number of data packets needed to transfer a group of reference pixel data. In one embodiment for reducing the reference data fetch bandwidth, the method as applied to a real-time video decoding system optimally combines pixel data stored in different memory pages, and fits the pixel data into a predetermined number of data packets.

Abstract: A graphics processing system has a cache which is partitionable into two or more slots. Once partitioned, the slots are dynamically allocatable to one or more texture maps. First, number of texture maps needed to render a given scene is determined. Then, available slots of the cache are allocated to the texture maps. Sometimes, more slots are allocated to the largest texture map. At other times, more slots are allocated to the texture map which is likely to be used most often. The slots can also be allocated equally to all of the texture maps needed.

Abstract: A system for processing graphics data for a stream of graphics primitives, such as triangles. The system has a plurality of memories each for storing an index of the primitive. A controller selects a memory to store the index and assigns a thread id to the index, the thread id indicating in which memory the index is stored. The thread id is stored in both a HEAD ID FIFO and a DATA ID FIFO, to maintain the order of the primitives during processing. A first multiplexer accesses a selected memory based on a thread id provided by the HEAD ID FIFO and a second multiplexer accesses a selected memory based on a thread id provided by the DATA ID FIFO. For each of the vertices of the graphics primitive, the first multiplexer provides a pointer for accessing coordinate information and the second multiplexer provides a pointer for accessing attribute information.

Abstract: A synchronized two-level cache including a level 1 cache and a level 2 cache is implemented in a graphics processing system. The level 2 cache is further partitioned into a number of slots which are dynamically allocated to texture maps as needed. The reference counter of each of the cache lines in each cache level is tracked so that a cache line is not overwritten with new data prior to transferring old data out to the recipient device. The age status of each cache line is tracked so that the oldest cache line is overwritten first. The use of a synchronized two-level cache system conserves system memory bandwidth and reduces memory latency, thereby improving the graphics processing system's performance.

Abstract: A system and method for providing shadow information for 3D computer graphics objects on a display for a graphic computer system are disclosed. The 3D objects are processed only once and the rendering and shadow generation information is stored in memory. In a subsequent two-dimensional pass, the shadow information is used to provide the color value at each rendered pixel. Thus, the latency and the need for storage capacity due to the multiple 3D pass processing are eliminated.

Abstract: A system and method for converting two binary digits into redundant sign-digit format. The system comprises a first adder for adding the binary digits together to generate a first result. A second adder adds an input carry from a previous digit to the first result and subtracts a value equal to the radix of the of the binary digits form the first result if the first result is greater than an initial threshold in order to generate an intermediate result. The system further includes a third adder for adding a second input carry from the previous digit to the intermediate result and subtracting the value of the radix from the intermediate result if the intermediate result is greater than a prescribed value such that the addition of the two binary digits are in redundant sign-digit format.

Abstract: A system for generating compensation pixel data for pixel data having adjacent values. The compensation pixel data is the pixel data adjusted by a value in order to perform an effect with the pixel data. The system has a comparator for determining whether the pixel data varies between adjacent values. Furthermore, the system includes a look-up table in communication with the comparator. The look-up table replaces the subsequent value of the pixel data with the compensation pixel data only when the preceding value of the pixel data is different than the subsequent value thereby reducing the number of look-ups for the compensation pixel data.

Abstract: A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different data item, where each different time interval is one of a plurality of successive, adjacent time intervals. Each unit provides an output data item in the time interval in which the unit performs the operation and provides a processed data item in the last of the successive, adjacent time intervals. The special function unit provides a special function computation for the output data item of a selected one of the scalar units, in the time interval in which the selected scalar unit performs the operation, so as to avoid a conflict in use among the scalar units. A vector processing unit includes an input data buffer, the scalar processor, and an output orthogonal converter.

Abstract: A parallel architecture for determining pixels inside a graphics primitive is provided. The architecture is a pipeline structure having a predetermined number of sequential logic circuits connected in series followed by a predetermined number of parallel logic circuits arranged in a pyramid structure. Each sequential logic circuit uses arithmetic edge functions corresponding to edges of a graphics primitive to determine whether a polygonal portion of a raster image is inside the graphics primitive. If the polygonal portion is at least partly inside the graphics primitive, the sequential logic circuit divides the polygonal portion into a predetermined number of subportions and computes descriptors (e.g., vertices and translated edge functions) for each subportion sequentially. Descriptors are then transferred sequentially to the next stage.

Abstract: A system and method is provided for preventing the occurrence of aliasing at the edges of polygons in 3D graphics. The system may detect both polygon geometric edges and Z edges due to intersection of multiple polygons. In one embodiment, the system includes an edge anti-aliasing module configured to selectively super-sample edge portions of primitives. The system further includes a coarse memory for storing information of pixels that are not super-sampled and a fine memory for storing information of pixels that are super-sampled by the edge anti-aliasing module.

Abstract: A method, apparatus and computer program product for parallel execution of primitives in 3D graphics engines. It includes detection and preservation of dependences between graphics primitives with the ability to execute multiple independent primitives concurrently while preserving their ordering because the architecture of the graphics engine for the present invention further provides concurrent resources for parallel execution. In a first preferred embodiment, primitives are executed in parallel using an in-order dispatch unit capable of detecting dependencies between primitives. In a second preferred embodiment, an out-of-order dispatch unit is used such that not only are primitives executed concurrently; but, the primitives may be executed in any order when dependencies are detected.

Abstract: An image processing system including an image encoder and image decoding system is provided. The image encoder system includes an image decomposer, a block encoder, and an encoded image composer. The image decomposer decomposes the image into blocks. The block encoder, which includes a selection module, a codeword generation module and a construction module, processes the blocks. Specifically, the selection module computes a set of parameters from image data values of a set of image elements in the image block. The codeword generation module generates codewords, which the construction module uses to derive a set of quantized image data values. The construction module then maps each of the image element's original image data values to an index to one of the derived image data values. The image decoding system reverses this process to reorder decompressed image blocks in an output data file.

Abstract: An image processing system including an image encoder and image decoding system is provided. The image encoder system includes an image decomposer, a block encoder, and an encoded image composer. The image decomposer decomposes the image into blocks. The block encoder, which includes a selection module, a codeword generation module and a construction module, processes the blocks. Specifically, the selection module computes a set of parameters from image data values of a set of image elements in the image block. The codeword generation module generates codewords, which the construction module uses to derive a set of quantized image data values. The construction module then maps each of the image element's original image data values to an index to one of the derived image data values. The image decoding system reverses this process to reorder decompressed image blocks in an output data file.

Abstract: Graphic processor compares z-buffer values of 3D objects to detect and mark interpenetrating pixels. Tag buffer stores marked values for antialiasing effectively by over-sampling, area-based, blending, alpha edge or other pixel-processing scheme. Performance is improved by selectively antialiasing at edges and/or interpenetrations. Cost is reduced by leveraging z-buffer storage therefor. Super-sampling antialiasing reduces sampling of select interpenetration elements, thereby avoiding processing entire image.

Abstract: A system and method for processing YCbCr video data stored in a paged memory with reduced page breaks. A method is disclosed for retrieving YCbCr planar video data in 4:2:0 format from paged memory. A page of the paged memory containing Y data is accessed; Y data corresponding to M pixels of video data is then retrieved, where M is a value greater than or equal to two. The retrieved Y data is then stored in a shift register. Similar steps are taken to access, retrieve and store Cb and Cr data. Within the shift register, the Y, Cb, and Cr data is stored as sets of planar video data. The Y, Cb, and Cr data is retrieved from the shift register as a series of pixel data for generating pixels on a video display unit.

Abstract: A system and method is provided for decreasing the amount of data required to represent depth information for 3D images. In accordance with one embodiment, depth information is represented by a piecewise function Z(x,y). An (x,y) space is split into areas representing a region of primitive shapes. For each of these regions, Z(x,y) is defined as a simple parametric analytical function. Subsequently, only a few parameters are required to encode this function in each region. By using these parametric analytical functions to represent depth value of the split, the present invention achieves advantages such as reductions in required storage space and required bandwidth with a concomitant increase in processing speed.