Abstract: A method for enabling services and functionalities across device types and service providers within a communication device includes processing a first device function type, a first service type, and a first cost function from the device, obtaining a first firmware and communicating the first firmware to the communication device for execution, activating a first set of service enabling instructions to enable a first service and a first functionality associated with the first firmware when the first firmware is executed on the communication device, processing a second device function type, a second service type, and a second cost function from the device, obtaining a second firmware to be executed on the device, communicating the second firmware to the device, and activating a second set of service enabling instructions to enable a second service and a second functionality associated with the second firmware when the second firmware is executed on the device.

Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

Abstract: A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.

Abstract: A method for enabling services and functionalities across device types and service providers within a communication device includes processing a first device function type, a first service type, and a first cost function from the device, obtaining a first firmware and communicating the first firmware to the communication device for execution, activating a first set of service enabling instructions to enable a first service and a first functionality associated with the first firmware when the first firmware is executed on the communication device, processing a second device function type, a second service type, and a second cost function from the device, obtaining a second firmware to be executed on the device, communicating the second firmware to the device, and activating a second set of service enabling instructions to enable a second service and a second functionality associated with the second firmware when the second firmware is executed on the device.

Abstract: A system for controlling an RF gain of a receiver that reduces a time taken to maintain an input signal level at an optimum dynamic range is provided. The system includes a tuner that receives a radio frequency (RF) signal and down-converts the RF signal to an intermediate frequency (IF) signal, and a demodulator. The tuner includes a radio frequency programmable gain amplifier (RF_VGA), a filter and an IF programmable gain amplifier (IF_VGA). The demodulator includes an analog to digital converter (ADC), and an Automatic Gain Control (AGC) unit that (i) receives a digital signal and an IF gain of the IF_VGA. The ADC samples a filtered IF signal under oversampling conditions to obtain an oversampled signal that includes an in-band signal and an out-of-band signal. The AGC unit (ii) controls the RF_VGA, the IF_VGA and (iii) measures an RF energy of the RF signal.

Abstract: A wide band receiver to select and demodulate an input signal with single scan spectrum sensing by performing filtering on the input signal in digital domain to achieve improved selectivity and sensitivity is provided. The input signal includes one or more narrowband radio frequency (RF) signals. The wide band receiver includes a wide band tuner that down converts the one or more narrowband RF signals to one or more IF signals. An analog to digital converter (ADC) converts the one or more IF signals to one or more digital signals. A filter rejects out-of-band signals from the one or more digital signals to achieve the improved selectivity. A numeric controlled oscillator (NCO) selects at least one narrowband digital signal from the digital signals based on a phase value obtained from a spectrum selection control unit. A demodulator demodulates the narrowband digital signal to obtain a demodulated digital signal.

Abstract: A receiver for reducing acquisition time of a Carrier Frequency Offset (CFO) of an input intermediate frequency (IF) signal with M-PSK modulated preamble using spectral based analysis is provided. The receiver includes an analog to digital converter that converts the input IF signal into a digital signal, a down conversion unit that down converts the digital signal to a baseband complex signal, and a CFO estimation block that estimates the CFO. The CFO estimation block includes a carrier harmonic generation unit that generates an output of carrier Mth harmonic without modulation in the baseband complex signal, a spectral mapping unit that spectrally maps the carrier harmonic using complex Fast Fourier Transform, a spectral analysis unit that performs peak search on the spectrally mapped carrier Mth harmonic to obtain a peak position (PPOS), and a carrier frequency offset estimation unit that receives the peak position (PPOS) and estimates the CFO.

Abstract: A vector slot processor that is capable of supporting multiple signal processing operations for multiple demodulation standards is provided. The vector slot processor includes a plurality of micro execution slot (MES) that performs the multiple signal processing operations on the high speed streaming inputs. Each of the MES includes one or more n-way signal registers that receive the high speed streaming inputs, one or more n-way coefficient registers that store filter coefficients for the multiple signal processing, and one or more n-way Multiply and Accumulate (MAC) units that receive the high speed streaming inputs from the one or more n-way signal registers and filter coefficients from one or more n-way coefficient registers. The one or more n-way MAC units perform a vertical MAC operation and a horizontal multiply and add operation on the high speed streaming inputs.

Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

Abstract: A system for computing a block floating point scaling factor by detecting a dynamic range of an input signal in a central processing unit without additional overhead cycles is provided. The system includes a dynamic range monitoring unit that detects the dynamic range of the input signal by snooping outgoing write data and incoming memory read data of the input signal. The dynamic range monitoring unit includes a running maximum count unit that stores a least value of a count of leading zeros and leading ones, and a running minimum count that stores a least value of the count of trailing zeros. The dynamic range is detected based on the least value of the count of leading zeros and leading ones and the count of trailing zeros. The system further includes a scaling factor computation module that computes the block floating point (BFP) scaling factor based on the dynamic range.

Abstract: A wide band receiver to select and demodulate an input signal with single scan spectrum sensing by performing filtering on the input signal in digital domain to achieve improved selectivity and sensitivity is provided. The input signal includes one or more narrowband radio frequency (RF) signals. The wide band receiver includes a wide band tuner that down converts the one or more narrowband RF signals to one or more IF signals. An analog to digital converter (ADC) converts the one or more IF signals to one or more digital signals. A filter rejects out-of-band signals from the one or more digital signals to achieve the improved selectivity. A numeric controlled oscillator (NCO) selects at least one narrowband digital signal from the digital signals based on a phase value obtained from a spectrum selection control unit. A demodulator demodulates the narrowband digital signal to obtain a demodulated digital signal.

Abstract: A receiver for reducing acquisition time of a Carrier Frequency Offset (CFO) of an input intermediate frequency (IF) signal with M-PSK modulated preamble using spectral based analysis is provided. The receiver includes an analog to digital converter that converts the input IF signal into a digital signal, a down conversion unit that down converts the digital signal to a baseband complex signal, and a CFO estimation block that estimates the CFO. The CFO estimation block includes a carrier harmonic generation unit that generates an output of carrier Mth harmonic without modulation in the baseband complex signal, a spectral mapping unit that spectrally maps the carrier harmonic using complex Fast Fourier Transform, a spectral analysis unit that performs peak search on the spectrally mapped carrier Mth harmonic to obtain a peak position (PPOS), and a carrier frequency offset estimation unit that receives the peak position (PPOS) and estimates the CFO.

Abstract: A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Abstract: In one embodiment, a Television (TV) receiver to perform a method of synchronizing a demodulator at a Viterbi decode input in the TV receiver using one or more bit de-interleaved even and odd Orthogonal Frequency Division Multiplexing (OFDM) symbols is provided. The method includes (i) performing a Viterbi decoding on the bit de-interleaved even and odd OFDM symbols when a frame boundary does not exist for the bit de-interleaved even and odd OFDM symbols, (ii) performing a convolutional encoding on an decoded data output of the Viterbi decoding, (iii) determining whether an output of the convolutional encoding of the bit de-interleaved OFDM symbols matches an input at a Viterbi decode, and (iv) determining whether the output of the convolutional encoding of the bit de-interleaved even and odd OFDM symbols matches with a SYNC pattern or a SYNC? pattern to obtain a RS packet align boundary.

Abstract: A system for controlling an RF gain of a receiver that reduces a time taken to maintain an input signal level at an optimum dynamic range is provided. The system includes a tuner that receives a radio frequency (RF) signal and down-converts the RF signal to an intermediate frequency (IF) signal, and a demodulator. The tuner includes a radio frequency programmable gain amplifier (RF_VGA), a filter and an IF programmable gain amplifier (IF_VGA). The demodulator includes an analog to digital converter (ADC), and an Automatic Gain Control (AGC) unit that (i) receives a digital signal and an IF gain of the IF_VGA. The ADC samples a filtered IF signal under oversampling conditions to obtain an oversampled signal that includes an in-band signal and an out-of-band signal. The AGC unit (ii) controls the RF_VGA, the IF_VGA and (iii) measures an RF energy of the RF signal.

Abstract: A receiver system for early detection of a segment type of an input signal based on BPSK and DBPSK modulated carriers is provided. The receiver system includes a tuner that converts the input signal into an intermediate frequency (IF) signal, a signal conditioning module that converts the IF signal into a baseband signal, a Frequency Domain Synchronisation (FDS) block that detects the segment type of the input signal based on a carrier powers, a Transmission and Multiplexing Configuration Control (TMCC) decode block that performs a decoding operation on the received signal, a channel estimation block that estimates a channel and obtains a channel information. The TMCC decode block uses the channel information obtained from channel estimation block to correct a fast-frequency selective fading on the received signal before the decoding operation.