Abstract: A system and method for dynamically switching transmission of selected data from cellular core network to unidirectional point-to-multipoint downlink network or from unidirectional point-to-multipoint downlink network to cellular core network based on traffic flow analysis is provided. The system includes a cellular packet core 206, a broadcast offload packet core (BO-PC) 302, and a load manager 202. The cellular packet core 206 controls a cellular radio access network (RAN) 412 for providing bidirectional connectivity to a converged user equipment (UE) (204) to transmit or receive selected data through the cellular packet core 206 and the RAN 412. The BO-PC 302 controls a broadcast radio access network (RAN). The broadcast radio access network (RAN) includes at least one Broadcast Radio Head (BRH) 322 for providing unidirectional downlink path to the converged user equipment (UE) 204 to receive selected data through the at least one Broadcast Radio Heads (BRH) 322.

Abstract: A system for improving indoor coverage of cellular reception is provided. The system includes an Intelligent receiver and a Pico transmitter. The intelligent receiver demodulates a signal received from a Broadcast radio head (BRH) with a HPHT or a LPLT toplogy through an outdoor high gain rooftop antenna that is externally connected to the intelligent receiver. The intelligent receiver includes an artificial intelligence (AI) or Machine learning (ML) based indoor coverage monitoring unit and a Pico transmitter application. The AI/ML based indoor coverage monitoring unit continuously monitors cellular reception factors of indoor user devices. The AI/ML based indoor coverage monitoring unit predicts an optimal indoor modulation profile and selects a required modulation index required for the indoor user devices. The Pico transmitter application re-broadcasts or relays the demodulated signal, based on an optimal indoor modulation profile required for the indoor user devices.

Abstract: A system for dynamically offloading data and video traffic to a broadcast offload core network from a cellular network or to the cellular network from the broadcast offload core network is provided. The system includes an analytics engine, a load manager, and a radio access network (RAN). The analytics engine captures geographical radio frequency (RF) information from a geographical RF information database. The geographical RF information includes an operator infrastructure information, a physical terrain information, a subscriber information, a coverage information, a signal quality information, and telecom traffic patterns. The analytics engine determines whether to offload the data and the video traffic to at least one of a unidirectional downlink network from a unicast network or the unicast network from the unidirectional downlink network by analyzing a hybrid cellular user equipment from a particular geographical location trying to access the data or video content.

Abstract: In one embodiment, a processor performs a method of generating pipelined data read indexes and data write indexes for a Prime Factor Algorithm (PFA) Discrete Fourier Transform (DFT) without look-up tables. The processor is adapted to factorize an ‘N’ point PFA DFT into one or more mutually prime factors and zero or more non-prime factors, calculate a 0th column index for an ith row (Xi0), calculate an IndCor when the value of Xi0 equals zero and when a row number (i) does not equal zero, calculate Xij, generate the data read indexes, perform a DFT kernel computation on Lk point for the mutually prime factors and the non-prime factors, and generate the data write indexes for the mutually prime factors and the non-prime factors. Xij represents ith row and jth column of 2D input Buffer and enables a selection of a linear index from the 2D input buffer.

Abstract: An Orthogonal Frequency Division Multiplexing (OFDM) receiver system for improved pilotless detection of symbol boundary of a received OFDM symbols using M-ary Phase Shift Keying (M-PSK) modulated carriers as a cost function. The OFDM receiver includes a symbol boundary detection block that detects a symbol boundary of the received OFDM symbols. The symbol boundary detection block detects the symbol boundary by computing a cost function of a second order moment of the M-PSK modulated carriers. The receiver system detects the symbol boundary for unknown information on the received OFDM symbols.

Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

Abstract: A receiver and method of detecting a guard interval estimate accurately by performing an Nth order polynomial based non-linear quantization on a pre-estimated guard interval in a received Orthogonal Frequency Division Multiplexing (OFDM) signal in a receiver is provided. The pre-estimated guard interval is obtained by performing normalized auto-correlation on the received OFDM signal. The method includes (i) performing a rounding operation on (a) one or more mth coefficient of the polynomial and (b) the pre-estimated guard interval to obtain an indexing parameter ‘k’, and detecting the guard interval estimate based on (i) a value of k, and (ii) a guard interval from one or more guard intervals that are stored in a look up table. The guard interval estimate is detected in accordance with an equation: {tilde over (L)}=L[k?4], where ‘L’ is the guard interval stored in the look up table that corresponds to the value of k.

Abstract: A Television (TV) receiver for faster channel switch times between a plurality of broadcasting TV channels with reduced latency in overall demodulation cycle for multiple demodulation standards is provided. The TV receiver includes a tuner that receives the broadcasting TV channels from a broadcasting system, performs a tuning operation, and sets a desired frequency for each of the broadcasting TV channels during a channel scan operation. A demodulator demodulates each of the broadcasting TV channels and acquires one or more acquisition channel parameters of each of the broadcasting TV channels during the channel scan operation. An application processor is coupled to the demodulator via a low throughput interface. The application processor performs a read operation and a write operation of the acquisition channel parameters to memory mapped registers on the demodulator when a channel status switches from a first state to a second state.

Abstract: A Software Defined Radio (SDR) subsystem capable of supporting a multiple communication standards and platforms for modulation, demodulation and trans-modulation of an input signal is provided. The SDR subsystem includes a Signal Conditioning Cluster (SCC) unit that includes a signal conditioning CPU adapted for sample based signal processing, a Signal Processing Cluster (SPC) unit that includes a signal processing CPU adapted for block based signal processing, and a Channel Codec Cluster (CCC) unit that performs a channel encoding or a channel decoding operation.

Abstract: A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size. A program memory receives a Program Memory address to fetch an instruction packet. The program memory is closely coupled with the instruction buffer size to implement the zero overhead software pipelined (SFP) loop. The size of the zero overhead software pipelined (SFP) loop can exceed the instruction buffer size. A CPU control register includes a block count and an iteration count. The block count is loaded into a block counter and counts the plurality of instructions executed in the SFP loop, and the iteration count is loaded into an iteration counter and counts a number of iterations of the SFP loop based on the block count.

Abstract: A Television (TV) receiver for faster channel switch times between a plurality of broadcasting TV channels with reduced latency in overall demodulation cycle for multiple demodulation standards is provided. The TV receiver includes a tuner that receives the broadcasting TV channels from a broadcasting system, performs a tuning operation, and sets a desired frequency for each of the broadcasting TV channels during a channel scan operation. A demodulator demodulates each of the broadcasting TV channels and acquires one or more acquisition channel parameters of each of the broadcasting TV channels during the channel scan operation. An application processor is coupled to the demodulator via a low throughput interface. The application processor performs a read operation and a write operation of the acquisition channel parameters to memory mapped registers on the demodulator when a channel status switches from a first state to a second state.

Abstract: An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs Radix-2 branch metric computations, Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs Radix-2 Path metric computations, Radix-4 Path metric computations, best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.