Abstract: Pixel clock frequency and optimum sampling phase adjustment is an important requirement in Flat panel display monitors (FPDM) with an analog video interface. This invention proposes a new and more advanced method for frequency and optimum sampling phase determination. It is based on analyzing the content of the image to arrive at an optimum value of phase and frequency by directly optimizing image quality. The method differs from existing methods on two counts. First, no assumptions are needed about the precise value of expected frequency. Second, instead of following a two step approach of first determining frequency and then phase, this invention makes possible a single pass phase-frequency optimization.
Abstract: An interlaced television signal is derived from an interlaced 625 line, nominally 50 Hz field rate television signal, the derived television signal having perceived reduced line structure and reduced flicker. The field rate and the number of lines of the derived television signal are increased with respect to the field rate and the number of lines of the original television signal, such that perceived flicker and line structure in the derived television signal is reduced. The increase in the field rate and the increase in the number of lines in the derived television signal results in a horizontal scanning rate that does not substantially exceed twice the horizontal scanning rate of the original television signal while minimizing undesirable motion artifacts.
Type:
Grant
Filed:
May 10, 2000
Date of Patent:
July 22, 2003
Assignee:
Sage, Inc.
Inventors:
Donald S. Butler, Xu Dong, Jack J. Campbell
Abstract: A video adapter circuit for adapting analog video signals provided by a personal computer system designed to drive a CRT display monitor into signals appropriate for driving a flat panel display monitor. The video adapter circuit accepts analog video and synchronizing signals in any one of several scanning formats commonly utilized in personal computer systems and automatically detects the scanning format of the signals. An oscillator generates a clock signal that is synchronized with the HSYNC signal generated by the personal computer system. Each of the analog RGB video signals are amplified by a video amplifier and sampled, according to the clock signal, by a analog-to-digital converter. A controller circuit compresses the sampled video signals and stores the compressed data in a dual-port video frame memory at a rate determined by the scanning format.
Abstract: A video adapter circuit for adapting analog video signals provided by a personal computer system designed to drive a CRT display monitor into signals appropriate for driving a flat panel display monitor. The video adapter circuit accepts analog video and synchronizing signals in any one of several scanning formats commonly utilized in personal computer systems and automatically detects the scanning format of the signals. An oscillator generates a clock signal that is synchronized with the HSYNC signal generated by the personal computer system. Each of the analog RGB video signals are amplified by a video amplifier and sampled, according to the clock signal, by a digital-to-analog converter. A controller circuit compresses the sampled video signals and stores the compressed data in a dual-port video frame memory at a rate determined by the scanning format.
Abstract: A video adapter circuit for adapting analog video signals provided by a personal computer system designed to drive a CRT display monitor into signals appropriate for driving a flat panel display monitor. The video adapter circuit accepts analog video and synchronizing signals in any one of several scanning formats commonly utilized in personal computer systems and automatically detects the scanning format of the signals. An oscillator generates a clock signal that is synchronized with the HSYNC signal generated by the personal computer system. Each of the analog RGB video signals are amplified by a video amplifier and sampled, according to the clock signal, by an analog-to-digital converter. A controller circuit compresses the sampled video signals and stores the compressed data in a dual-port video frame memory at a rate determined by the scanning format.