Abstract: In the present invention the issue of calculating voltage drop at the contact points of the power network with injected power currents is proposed. The method consists of the three steps. First, the said power network is partitioned into sub-networks. Secondly, the said sub-networks are expressed in terms of their admittance matrices and voltage transfer functions, which are then fed into timing simulator handling both time and frequency to compute the voltage drop at the said contact points. To achieve better partition result, inputs, outputs including user assigned nodes for recording voltages, are utilized to absorb the sub-network without inputs and outputs into the same partition as its parent node, and generate output cone with single input and outputs. Timing simulator uses convolution to get input voltage at each time step recursively and then voltage transfer used to evaluate output voltage at the same time step with minimal computational overhead.

Abstract: A system and process of generating an improved image for optical character recognition is disclosed comprising dynamically obtaining a video source image comprising one or more characters on a background using a video capture device; detecting edges of at least one of the one or more characters that comprise the video source image; determining a sharpness value for the edges of the at least one of the one or more characters, wherein the sharpness value is related to the ability of the video capture device to distinguish the edges of the characters from the background; and indicating at least when the sharpness value is at a predetermined value or within a predetermined range of values.

Abstract: In the present invention the issue of SSTA in multi-phase sequential circuit with cross-talk in consideration of non-uniform timing constraint and process variations up to the 2nd order is proposed. Use forward breadth first search to calculate the accumulated probabilities at each node for clock phases and edge probability with respect to input and output clock phases, followed by backward depth first traversal to find all critical paths with their probabilities greater than user specified threshold. A method is proposed to pre-characterize the timing library including second order variations. For cross-talk, the poles and residues of admittance matrix and voltage transfer are carried out to 2nd order variations. Effective capacitances and waveforms at interconnect input or driver's immediate output are calculated to 2nd order variations. Delays at victim outputs are then calculated to 2nd order variations and fed back to SSTA, the probability of path occurrence can be calculated accurately.

Abstract: A system and process of nearsighted (myopia) camera object detection involves detecting the objects through edge detection and outlining or thickening them with a heavy border. Thickening may include making the object bold in the case of text characters. The bold characters are then much more apparent and heaver weighted than the background. Thresholding operations are then applied (usually multiple times) to the grayscale image to remove all but the darkest foreground objects in the background resulting in a nearsighted (myopic) image. Additional processes may be applied to the nearsighted image, such as morphological closing, contour tracing and bounding of the objects or characters. The bound objects or characters can then be averaged to provide repositioning feedback for the camera user. Processed images can then be captured and subjected to OCR to extract relevant information from the image.

Abstract: A system and process of nearsighted (myopia) camera object detection involves detecting the objects through edge detection and outlining or thickening them with a heavy border. Thickening may include making the object bold in the case of text characters. The bold characters are then much more apparent and heavier weighted than the background. Thresholding operations are then applied (usually multiple times) to the grayscale image to remove all but the darkest foreground objects in the background resulting in a nearsighted (myopic) image. Additional processes may be applied to the nearsighted image, such as morphological closing, contour tracing and bounding of the objects or characters. The bound objects or characters can then be averaged to provide repositioning feedback for the camera user. Processed images can then be captured and subjected to OCR to extract relevant information from the image.

Abstract: Access to features in a business context-based social network is provided based on verification of a provided association between a user's social network account and a verified social network account of an organizational entity. The association represents a relationship between the user and the organizational entity outside of the business context-based social network. Based on verification of the account of the organizational entity and on the provided association, access is enabled for the account of the user to one or more features offered by a social network account of another organizational entity in the business context-based social network. The access provided for the account of the user to the one or more features is authorized based on the provided association between the verified account of the organizational entity and the account of the user.

Abstract: Rule-based triggering of execution of services is provided. An advisor program identifies an application attribute(s) about which data is to be obtained, based on the presence of the application attribute(s) in one or more logical expressions of one or more rules. The one or more rules are developed and managed separate from the program code of the application and use at least one identifier employed by the application in identifying application attributes. Data about the application attribute(s), for instance user behavior with respect to the application attribute(s), is obtained, and the logical expression(s) of the rule(s) are evaluated based on the obtained data to determine whether to trigger execution of one or more services specified in the rule(s).

Abstract: In the present invention a method to address voltage drop effect in the path based timing analysis for multi-phase sequential circuit is proposed. In calculating the new delay of the gate along the specified path the fact that stored discrete arrival times with respect to different clock phases at each node is used to determine a set of gates that can have transitions overlapping with that of the said gate. Furthermore, the said set is reduced by the logic verification step. Two step approach is adopted, the first is to evaluate the power currents for the said reduced set of gates by using pre-characterized timing library, then use these currents to calculate new VDD of the said gate along the path and obtain new delay for this gate. Some cell may have several internal transitions, the process of modeling power currents in terms of several triangles is discussed.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.