Abstract: A method for protecting a non-volatile memory device, the method including forming a non-volatile memory device including a polycide structure formed over a non-conducting charge trapping layer, and forming a protective layer over at least a portion of the polycide structure, the protective layer being adapted to absorb electromagnetic wave energy having a wavelength shorter than visible light. A device constructed in accordance with the method is also disclosed.

Abstract: A mass storage device comprising at least one array of memory cells, at least one data path unit in communication with the at least one array, the at least one data path unit comprising a master buffer, and a main data bus adapted to transfer data between the at least one data path unit and an input/output (I/O) unit via a buffer interface unit (BIF) comprising a plurality of slave buffers, the main data bus being further adapted to support at least one of a download and upload of data between the main data bus and the I/O unit, during simultaneous performance of an internal operation between the main data bus and the at least one array, the internal operation comprising at least one of a read, program and erase operation. Methods for operating the mass storage device are also disclosed.

Abstract: A regulator circuit to deliver a regulated boosted voltage VPP from a charge pump to electrodes of the cells of a non-volatile memory (NVM) array, such as an EPROM, integrated circuit device. The regulator includes a differential amplifier operating from a VDD voltage lower than VPP that drives a gain stage whose output is to a current mirror operating from the boosted VPP voltage. The current mirror output is taken across a voltage divider as the regulated output of the circuit. The differential amplifier has one input at a fixed voltage and the other being a feedback voltage from the voltage divider to control the gain of the differential amplifier and thereby regulate the output of the gain stage and current mirror in response to a variable load current of the integrated circuit device.