Abstract: A display apparatus including a processor configured to control the display to display content according to a user input, obtain data associated with a usage state of a user based on image data captured by a camera and sensing values of at least one sensor, and based on the usage state being identified as suitable to measure biometric information based on data associated with the usage state of the user and an artificial intelligence model, newly obtain image data of the user through a camera, and obtain the biometric information based on the newly obtained image data of the user.

Abstract: A thin film deposition device according to embodiments includes a tube, a boat disposed within the tube and configured to load a plurality of wafers in parallel at spaced intervals, and a nozzle disposed within the tube along one direction and including a plurality of holes configured to supply a gas toward the wafers, wherein at least one of the plurality of holes has a diameter different from diameters of the others.

Abstract: A memory device includes one or more memory banks, and one or more operators disposed to access the one or more memory banks and configured to perform an operation on polynomial data, wherein, in response to the polynomial data being distributed to the one or more memory banks, the one or more operators are configured to perform parallel operations on the polynomial data, and in response to controlling data input/output between the one or more memory banks and the one or more operators, the one or more operators are configured to perform a modular operation and the one or more memory banks are configured to store a result of the modular operation.

Abstract: A storage device includes a nonvolatile memory device including an input/output register, the nonvolatile memory device sensing data from a memory region corresponding to an address and transmitting the data that is sensed from the memory region, and a storage controller that transmits a command and the address to the nonvolatile memory device via a first bus and that transmits and receives data to and from the nonvolatile memory device via a second bus. The nonvolatile memory device, in response to a first command that is received from the storage controller, outputs a sensing status of first data and stores the first data in the input/output register.

Abstract: The present disclosure provides a memory controller for managing memory access requests from a plurality of masters. The memory controller may include a master decoding engine configured to decode memory access response traffic for the plurality of masters, a master latency storage configured to store a plurality of latency parameters, per-master first-in-first-out (FIFO) buffers configured to store a plurality of responses pending transmission to a respective master, a timer module configured to determine elapsed time and to accumulate latency error statistics, an adaptive weight generation engine configured to receive the latency error statistics and to generate one or more arbitration weights for each of the plurality of masters based on the latency error statistics, and a weighted arbiter configured to arbitrate between the plurality of responses ready for transmission from the per-master FIFO buffers.

Abstract: A computing device for a multidimensional vector neural network includes: input lines to which multidimensional input vectors are input; output lines intersecting the input lines; memory cells disposed at intersecting points between the input lines and the output lines and configured to store weight elements included in multidimensional weight vectors; selectors configured to transmit a value output from each of the output lines to any one of adders; and the adders configured to accumulate values received from the selectors in a predetermined number of cycles, wherein, for each of the multidimensional weight vectors, weight elements included in the multidimensional weight vector are stored in reference memory cells that connect a corresponding single reference input line and corresponding two or more reference output lines.

Abstract: Provided is a display apparatus including a first semiconductor layer having a first surface and a second surface opposite to each other, a plurality of partitions protruding from the first surface, and a plurality of opening areas between the plurality of partitions, a plurality of active layers provided opposite to the plurality of opening areas on the second surface of the first semiconductor layer, a plurality of second semiconductor layers respectively provided on the plurality of active layers opposite to the first semiconductor layer, a separation film provided between two adjacent active layers among the plurality of active layers and between two adjacent second semiconductor layers among the plurality of second semiconductor layers, and a plurality of color conversion layers provided in the plurality of opening areas on the first surface of the first semiconductor layer.

Abstract: A light-emitting device may include a vertical stack structure including first to third epitaxial structures that are sequentially stacked, a separation layer on the third epitaxial structure, a plurality of nanostructures on the separation layer, and a background medium between the plurality of nanostructures, wherein each of the plurality of nanostructures may include a first layer and a second layer on the first layer.

Abstract: A method of performing load balancing in a control plane of a virtual wireless access network, includes: obtaining a packet from a client; searching for session information corresponding to the packet in a local table of at least one load balancer or a global table; updating at least one of the local table or the global table based on at least one of whether the session information exists in the local table or whether the session information exists in the global table; and transmitting the packet to a backend server identified according to a distribution method based on the session information.

Abstract: A handover method, a mobile handover apparatus and a wireless communication system are disclosed. The handover method includes obtaining first position information of a user equipment, determining whether the user equipment is in a handover area of a first cell of the base station based on the first position information, transmitting a reference signal measurement request to the user equipment in response to determining the user equipment is in the handover area, receiving reference signal strength information from the user equipment, the reference signal strength information corresponding to the reference signal measurement request, and handing over the user equipment from the first cell to a target cell adjacent to the first cell.

Abstract: Provided are an interposer capable of early testing for defects without using an intermediate medium, a semiconductor package including the interposer, and a testing method for the interposer. The interposer includes a body layer, a wiring layer disposed on the body layer, a through post penetrating through the body layer, an interposer pad disposed on the wiring layer, and a test pad disposed on a connection area of the wiring layer and connected to a part of the interposer pad.

Abstract: A semiconductor package is provided. The semiconductor package includes a substrate, a first semiconductor chip provided on an upper surface of the substrate, an interposer provided on the first semiconductor chip, a conductive pad provided on the upper surface of the substrate, and a connecting portion provided between the upper surface of the substrate and a lower surface of the interposer. The connecting portion is spaced apart from the first semiconductor chip along a horizontal direction parallel to the upper surface of the substrate and electrically connects the conductive pad and the interposer. The connecting portion includes a metal post that extends in a vertical direction perpendicular to the upper surface of the substrate and a first metal layer that surrounds a surface of the metal post. The first metal layer and the metal post include different metals.

Abstract: A refrigerator includes a main body including a storage compartment, a door configured to rotate to open or close the storage compartment, a door driving device configured to open or close the door, a communication interface configured to communicate with an external device, and a controller configured to receive setting information from the external device through the communication interface, the setting information including at least one received setting information item among setting information items to set a door opening speed, a door closing speed, an opening time delay from a time point at which an opening condition is satisfied, or a closing time delay from a time point at which a closing condition is satisfied, and control the door driving device such that the door is opened or closed, based on the opening or closing condition being satisfied, and according to the at least one received setting information item.

Abstract: A refrigerator includes an inner case having a storage compartment therein, an outer case outside the inner case, and an injection molded insulating member in a spaced region between the inner case and the outer case. The injection molded insulating member includes an insulating panel and an insulating material integrally formed together. The insulating material surrounds at least a portion of the insulating panel.

Abstract: A storage device includes a plurality of non-volatile memories, and a storage controller connected to the plurality of non-volatile memories through a data line and a command address line separated from the data line. The plurality of non-volatile memories are respectively configured to transmit peak current information through the command address line after on die termination (ODT) for all of the plurality of non-volatile memories is disabled.

Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine, a link ECC engine. The link ECC engine, in a write operation, receives a first codeword including a first main data and a first link parity data from a memory controller, generates a first syndrome including a plurality of syndrome bits based on the first codeword and a first parity check matrix that is based on a first ECC, generate a decoding status flag indicating whether a transmission error is detected in the first codeword using a characteristic of the first syndrome based on a regularity of the first parity check matrix while decoding the first syndrome, corrects an error bit of the first codeword based on the decoded first syndrome, and provides the first main data of the first codeword, which is corrected, to the on-die ECC engine.

Abstract: A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit including sub peripheral circuits under the sub cell arrays. The sub peripheral circuits are divided into first and second column edge regions and a central region. The central region is between the first column edge region and the second column edge region. A sense amplifier region including a plurality of bitline sense amplifiers are disposed in at least one of the first column edge region and the second column edge region. A wordline driver region including a plurality of sub wordline drivers is disposed in the central region. At least a portion of device peripheral circuits configured to control the memory core circuit is disposed in a rest region other than the sense amplifier region and the wordline driver region.

Abstract: According to embodiments, a semiconductor device comprising: a substrate including a first surface and a second surface opposing one another; a first conductivity type semiconductor layer positioned on the first surface of the substrate; a second conductivity type doped well region positioned within the first conductivity type semiconductor layer; a pillar layer positioned between the substrate and the second conductivity type doped well region and having the second conductivity type; a gate electrode positioned on the first conductivity type semiconductor layer; a gate insulating layer positioned between the first conductivity type semiconductor layer and the gate electrode; a source electrode positioned on the second conductivity type doped well region; and a drain electrode positioned on the second surface of the substrate, the pillar layer includes a first pillar pattern including a semiconductor material having a first energy band gap, and a second pillar pattern positioned between the first pillar patte

Abstract: An image sensor according to at least one example embodiment includes a substrate, a plurality of pixel regions, and a wiring portion electrically connected to the plurality of regions. Each of the plurality of pixel regions includes a photodiode in the substrate and a pixel circuit at a first surface of the substrate. The wiring portion includes a capacitor. The capacitor includes a plurality of electrodes and an insulation layer between the plurality of electrodes. The plurality of electrodes include a first electrode group and a second electrode group electrically insulated from each other. At least one of the first electrode group and the second electrode group includes a plurality of electrode layers electrically connected to each other. The capacitor includes a side overlap portion in which the first electrode group and the second electrode group are stacked at a side surface of the capacitor.

Abstract: A light-emitting diode comprising a metal pad; a first sub-pixel, arrangeable on the metal pad, to emit light of a first color; a second sub-pixel emitting light of a second color different from the light of the first color; and a third sub-pixel emitting light of a third color different from the light of the first color from the first sub-pixel and the light of the second color from the second sub-pixel.