Abstract: A method and apparatus for implementing a prefetch scheme in which a plurality of data are simultaneously read from memory cells of sequential addresses synchronized to an external signal and serially transferred from the memory cells to a temporary latch circuit which has a number of bits corresponding to the member of bits in the prefetch scheme. The bits in the temporary latch circuit are multiplexed and sequentially driven out of the memory device. The memory device includes a plurality of memory cells which are connected to an input/output line pair through a plurality of column select gates, each of which is controlled by an independent chip select line. A sense amplifier is connected to the input/output line pair for sensing and amplifying data from the input/output lines and to transmit data to the input/output lines. A data output buffer transfers the data from the sense amplifier to the outside of chip.