Abstract: A data output buffer includes an output driving stage having a pair of parallel pull-up transistors and a pull-down transistor, a latch circuit for latching a pair of complementary signals, a second gate for gating the non-inverted output signal of the latch circuit in response to an external output enable signal and then supplying it to the gate of one pull-up transistor of the output driving state, a third gate also for gating the non-inverted output signal of the latch circuit in response to an external output enable signal, and a selective bootstrap circuit for driving the other pull-up transistor of the output driving stage. The output driving stage is driven to an external supply voltage when the external supply voltage is higher than a set voltage, and is driven to a boosted voltage when the external supply voltage is lower than the set voltage, determined by output signals from the second and third gates.