Abstract: A sampling circuit includes a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal, a first switch connected between the first input terminal and the linearization circuit, a second switch connected between the first input terminal and the linearization circuit, a third switch connected between the second input terminal and the linearization circuit, a fourth switch connected between the second input terminal and the linearization circuit, a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampled signal, and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampled signal.

Abstract: A charging circuit may include a buck-boost circuit and a voltage regulator circuit, wherein the buck-boost circuit converts a first input voltage received at a first node into a first output voltage and charges a battery based on the first output voltage, and time-divisionally converts a second input voltage provided from the battery into a second output voltage provided to a first external device and a third output voltage provided to a second external device, and the voltage regulator circuit adjusts the first input voltage to generate the second output voltage and the third output voltage.

Abstract: A method of operating a base station, includes: transmitting a reference signal to an electronic device comprising a first model and a third model; receiving a first intermediate output from the electronic device; obtaining a second intermediate output by inputting the first intermediate output to a partial model excluding an output layer from a second model comprising a second neural network for data decompression; transmitting the second intermediate output to the electronic device; receiving a first gradient value from the electronic device and updating weight parameters of the partial model; and generating a second gradient value different from the first gradient value and transmitting the second gradient value to the electronic device.

Abstract: A terminal receives a measurement configuration from a serving cell, measures at least one received signal based on the measurement configuration, and confirms whether an event corresponding to the measurement configuration has occurred. Based on the confirming that the event has occurred, the terminal generates a latent vector by encoding a measurement result set including a plurality of measurement results, and in response to the occurrence of the event, transmits, to the serving cell, a measurement report generated based on the latent vector.

Abstract: A memory device is provided. The memory device includes: a buffer memory; a nonvolatile backup memory; and a memory controller configured to: store map data corresponding to an external storage device in the buffer memory; provide, in response to a request from the external storage device, an address pair corresponding to the request, from among address pairs of the map data, to the external storage device; and back up, in response to a sudden power-off event, the map data to the nonvolatile backup memory.

Abstract: A semiconductor device includes a first active pattern extending in a first direction, a second active pattern on the first active pattern and extending in the first direction, a gate structure on the first active pattern and the second active pattern and extending in a second direction intersecting the first direction, a first source/drain region on side faces of the gate structure and connected to the first active pattern, a second source/drain region on the side faces of the gate structure and connected to the second active pattern, and an intermediate connecting layer which includes a first intermediate conductive pattern between the first active pattern and the second active pattern, and a second intermediate conductive pattern connected to the first intermediate conductive pattern between the first source/drain region and the second source/drain region.

Abstract: There is provided an image sensor including a substrate, a plurality of pixel groups respectively including a plurality of photodiodes provided in the substrate, a pixel isolation pattern provided between the plurality of photodiodes in the substrate, an auxiliary isolation pattern provided to extend inside from a surface of the substrate, and a micro lens provided on the surface of the substrate. The pixel isolation pattern includes an outer isolation pattern provided between the plurality of pixel groups and an inner isolation pattern provided between the plurality of photodiodes within the plurality of pixel group, and the auxiliary isolation pattern is provided between the outer isolation pattern and the inner isolation pattern that are spaced apart from each other or between a plurality of inner isolation patterns that are spaced apart from each other.

Abstract: An image sensor includes a substrate, a plurality of photodiodes in the substrate, a pixel separating pattern in the substrate separating the plurality of photodiodes, a first active pattern in the substrate at least partially overlapping a first photodiode and a second photodiode from among the plurality of photodiodes, a selection gate on the first active pattern at least partially overlapping the first photodiode, and a source follower gate on the first active pattern at least partially overlapping the second photodiode. The first photodiode is adjacent to the second photodiode. The pixel separating pattern includes a first pixel separating pattern and a second pixel separating pattern disposed between the first photodiode and the second photodiode. The first pixel separating pattern is spaced from the second pixel separating pattern. The first active pattern includes a first extrinsic region disposed between the first pixel separating pattern and the second pixel separating pattern.

Abstract: A memory device includes: first conductive lines extending in a first horizontal direction on a substrate; second conductive lines extending on the first conductive lines in a second horizontal direction; third conductive lines extending on the second conductive lines in the first horizontal direction; first memory cells provided at portions where the first conductive lines cross the second conductive lines; second memory cells provided at portions where the second conductive lines cross the third conductive lines; first dummy patterns horizontally spaced apart from the first memory cells and the second memory cells; and second dummy patterns horizontally spaced apart from the first memory cells and the second memory cells, the second dummy patterns facing the first dummy patterns, respectively, in the second horizontal direction. The plurality of first dummy patterns and the plurality of second dummy patterns are on different vertical levels from each other.

Abstract: An image sensor includes a plurality of pixels arranged in a matrix form, photodiodes for the respective pixels, the photodiodes within a semiconductor substrate having a first surface to which light is incident and a second surface that faces away from the first surface, micro lenses over the first surface of the semiconductor substrate and configured to concentrate the light, color filters between the semiconductor substrate and the micro lenses, and an optical path changing member configured to change a path of at least a portion of the light when the light travels toward the photodiodes through the micro lenses. The optical path changing member having a curved surface being concave or convex on the first surface of the semiconductor substrate.

Abstract: An image sensor includes a pixel array in which pixels having photoelectric conversion elements are arranged in a matrix, color filters corresponding to the pixels and configured to selectively transmit light of at least two different wavelength bands, and microlenses on the color filters. At least some of the microlenses may have different shapes depending on respective wavelength bands that respective corresponding color filters at least partially overlapping with the at least some microlenses are configured to selectively transmit, such that the at least some microlenses are configured to compensate for chromatic aberration between the lights passing through the respective corresponding color filters.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure on the substrate, the gate structure extending across the active region in a first horizontal direction, bit line structures on bit line trenches extending in a second horizontal direction, intersecting the first horizontal direction, the bit line trenches on an upper surface of the substrate across the gate structure, contact plugs between the bit line structures, landing pad structures on the contact plugs, and an insulating pattern between the landing pad structures, the insulating pattern in contact with the bit line structures. Portions of the bit line structures extend in the second horizontal direction in the bit line trenches. Each of the landing pad structures includes a lower landing pad, arranged on a level lower than that of each of upper surfaces of the bit line structures, and an upper landing pad on the lower landing pad.

Abstract: A semiconductor integrated circuit device includes a standard cell on a substrate, an one time programmable (OTP) memory structure at an edge portion of the standard cell, and a program transistor outside of the standard cell at a position adjacent to the edge portion of the standard cell at which the OTP memory structure is provided, the program transistor being electrically connected to the OTP memory structure. The OTP memory structure includes a first anti-fuse and a second anti-fuse. When a program voltage is applied to the program transistor and a bias power voltage is applied to the OTP memory structure, each of the first anti-fuse and the second anti-fuse becomes shorted and the bias power voltage is provided to the standard cell.

Abstract: A light emitting element is provided. The light emitting element includes: a light emitting stack including an active layer between an N-type nitride semiconductor layer and a P-type nitride semiconductor layer, the light emitting stack having a width of 5 nm or more and 200 ?m or less; a first electrode connected to the N-type nitride semiconductor layer; and a second electrode connected to the P-type nitride semiconductor layer. The P-type nitride semiconductor layer has a first surface, adjacent to the active layer, and a second surface, opposite to the first surface, and includes AlxInyGazN (0?x<1, 0?y<1, 0<z?1), and a bandgap of the p-type nitride semiconductor layer does not increase in a stacking direction from the second surface to the first surface. The N-type nitride semiconductor layer includes a superlattice layer and an electron retardation layer.

Abstract: A method and apparatus for measuring properties of a magnetic body are provided. The method includes applying a uniform magnetic field to generate a magnetic space; rotating a magnetic body in the magnetic space about a predetermined axis; measuring a first resistance value; measuring a second resistance value; and calculating a magnetic anisotropy constant of the magnetic body, based on the first and second resistance values, wherein the first resistance value is a measured resistance value of the magnetic body according to a magnetic field sweep in a direction of a magnetization hard axis of the magnetic body, and wherein the second resistance value is another measured resistance value of the magnetic body according to an angle of an external magnetic field, the angle of the external magnetic field being an angle formed by a magnetization easy axis of the magnetic body and a direction of the uniform magnetic field applied to the magnetic body.

Abstract: A semiconductor memory device is provided. The semiconductor device includes: a stacked structure with word line plates and mold insulating layers which extend in first and second horizontal directions, and are alternately stacked in a vertical direction in a cell array region and an extension region, the plurality of word line plates forming a staircase structure in the extension region; a vertical bit line extending into the stacked structure in the cell array region; a plurality of selection layers between the plurality of word line plates and the vertical bit line; and a vertical channel transistor connected to one end of the vertical bit line. A first thickness of each of the plurality of mold insulating layers is about 1.5 times to about 3 times a second thickness of each of the plurality of word line plates.

Abstract: A chemical mechanical polishing apparatus includes: a platen; a chemical mechanical polishing (CMP) pad on an upper surface of the platen, the CMP pad comprising an installation hole; a polishing head on the platen, the polishing head being configured to bring a wafer W into contact with the CMP pad; a slurry supply unit configured to supply slurry to the CMP pad; and a sensor module in the installation hole of the CMP pad, wherein the sensor module includes: a window at an upper end of the installation hole; a housing below the window, the housing comprising an inclined internal surface; and a sensor below the housing.

Abstract: The dishwasher may comprise: a tub forming a washing chamber; a spray unit for spraying water into the washing chamber; a sump to accommodate the water to be supplied to the spray unit; and a duct including a first body part, which extends along a first direction and is connectable to the spray unit, and a second body part, which extends from the first body part in a second direction and allows the water from the sump to be introduced. The duct can include: a first frame including a plurality of first coupling members aligned in the first direction and the second direction; a second frame including a plurality of second coupling members that can be coupled to the plurality of first coupling members; a guide path formed by the coupling of the first frame and the second frame; and a partition to partition the guide path into a plurality of sections.

Abstract: A semiconductor memory device comprises a cell structure and a peripheral circuit structure electrically connected to the cell structure. The peripheral circuit structure comprises an active region, a first gate structure comprising a first gate insulating layer intersecting the active region and in contact with the active region, a second gate structure comprising a second gate insulating layer spaced apart from the first gate structure, and in contact with the active region, and a source/drain region between the first gate structure and the second gate structure. A thickness of the first gate insulating layer is less than a thickness of the second gate insulating layer. The source/drain region comprises a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. A depth of the first region is equal to a depth of the second region.

Abstract: A connecting apparatus arrangeable to connect a display and a stand. The connecting apparatus includes a plurality of coupling protrusions arrangeable at the display, and a mounting unit connectable to the stand, the mounting unit including a plurality of hooks coupleable to the plurality of coupling protrusions, respectively, so that while the plurality of hooks of the mounting unit that is connected to the stand are coupled to the plurality of coupling protrusions which are arranged at the display, the display and the stand are connected to each other, and at least a number of hooks from among the plurality of hooks are moved along a first direction to couple to the plurality of coupling protrusions and are moved along a second direction opposite the first direction to decoupleable from the plurality of coupling protrusions.