Abstract: A housing of an electronic device includes a base layer, a first visible layer provided on a first surface of the base layer, and a second visible layer provided on a second surface of the base layer. The second visible layer is non-visible from an outside of the electronic device in a first illumination environment and where the first visible layer and the second visible layer are visible from the outside of the electronic device in a second illumination environment.

Abstract: A semiconductor device includes a first Low Noise Amplifier (LNA), a second LNA, first and second receiving circuits, an a radio frequency multiplexer. The first LNA is connected to a first receiving port, and the second LNA is connected to a second receiving port different from the first receiving port. The first receiving circuit includes a first transformer and processes one or more outputs of the first and second LNAs. The second receiving circuit processes one or more of the outputs of the first and second LNAs. The radio frequency multiplexer controls connection between the first and second LNAs and the first and second receiving circuits. The first receiving circuit includes a first variable capacitor having a first end connected to an output of the radio frequency multiplexer and a second end connected to the first transformer.

Abstract: An image encoding method based on artificial intelligence (AI) includes obtaining motion vector feature data of a current frame by inputting the current frame and a reference frame to a motion vector encoder and applying a plurality of resolution scales to the current frame and the reference frame via the motion vector encoder; obtaining a current motion vector by inputting the motion vector feature data to a motion vector decoder; obtaining a current predicted image based on the current motion vector and the reference frame; and generating a bitstream based on the motion vector feature data and the current predicted image.

Abstract: A device may include processing circuitry configured to, generate a device identifier associated with the device, and generate a unique endorsement identity (ID) associated with the device identifier, a first layer sub-circuit configured to, receive the device identifier, and generate a first certificate and a second certificate based on the device identifier and the unique endorsement ID, the first certificate and the second certificate including information to authenticate the device, and the processing circuitry is further configured to, receive the first certificate and the second certificate, and verify whether the device has been modified based on the first certificate and the second certificate, wherein, in response to the first layer sub-circuit being modified, the first layer sub-circuit is further configured to, generate an endorsement key based on a new unique endorsement ID, and generate a certificate signing request for the new unique endorsement ID based on the endorsement key.

Abstract: A compound represented by Chemical Formula 1, and near-infrared absorbing/blocking films, photoelectric devices, organic sensors, and electronic devices including the compound are provided: wherein, in Chemical Formula 1, X1 to X4, and R1 to R9 are the same as defined in the detailed description.

Abstract: A semiconductor memory may include a substrate, a buried dielectric layer on the substrate and providing a first recess that extends in a first direction, a word line in the first recess of the buried dielectric layer, first and second source/drain patterns on opposite sides of the word line, a channel pattern between the word line and the first recess of the buried dielectric layer and contacting the first and second source/drain patterns, and a bit line electrically connected to the second source/drain pattern and extending in a second direction that intersects the first direction. The channel pattern includes vertical parts and a horizontal part connected to each other. The vertical parts are on opposite lateral surfaces of the word line. The horizontal part is below the word line.

Abstract: Disclosed are a device and method with memory request processing using an extension of a memory address space. An electronic device includes a host processor configured to generate a memory request and a memory address that is mapped to a target memory mode that is any one of available memory modes and is mapped to a physical memory address to which the memory request is to be applied, a memory controller configured to generate the physical memory address and a command according to the target memory mode mapped to the memory address based on the memory request and the memory address received from the host processor, and a memory configured to execute, at the physical memory address, the command received from the memory controller.

Abstract: A sensor device includes: a support structure having a cantilever shape extending in a first direction and having a first end fixed; a sensing element having a surface and a resonant frequency changing according to contaminants adsorbed to the surface and disposed at a second end of the support structure; a frequency detector configured to detect the resonant frequency of the sensing element; and an actuator disposed at the one end of the support structure and configured to move the support structure so that the second end of the support structure moves in a second direction perpendicular to the first direction.

Abstract: A storage device, including a nonvolatile memory device including a plurality of memory cells forming a user area and a reserved area; and a controller configured to perform a write operation on at least one write unit included in the plurality of memory cells, and to perform an erase operation on at least one erase unit included in the plurality of memory cells, wherein the controller includes an internal buffer, wherein the controller is configured to: perform a backup operation by writing first data stored in the internal buffer in a backup erase unit included in the reserved area, and after performing the backup operation adjust a buffering unit of the internal buffer to correspond to a cell type of the backup erase unit.

Abstract: A method of manufacturing an integrated circuit device includes preparing a semiconductor substrate having an active area and a field area, sequentially forming a lower insulation layer, a buried layer, a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer on the semiconductor substrate, removing a portion of the third sacrificial layer to form a first sacrificial pattern, removing a portion of the second sacrificial layer and the first sacrificial pattern to form a second sacrificial pattern, removing a portion of the first sacrificial layer and the second sacrificial pattern to form a third sacrificial pattern, removing a portion of the buried layer and the third sacrificial pattern to form a buried pattern, and removing a portion of the lower insulation layer and a portion of the semiconductor substrate by using the buried pattern as an etch mask to form a word line trench.

Abstract: Provided is a semiconductor package. The semiconductor package including a redistribution structure including a plurality of redistribution conductive patterns, a plurality of conductive vias connected to at least one of the plurality of redistribution conductive patterns, a plurality of lower pads connected to the plurality of conductive vias, and a plurality of redistribution insulation layers and the plurality of redistribution conductive patterns alternating each other, a semiconductor chip arranged on the redistribution structure, and an external connection terminal attached to the plurality of lower surface pads of the redistribution structure, wherein each of the plurality of redistribution conductive patterns includes a metal layer including copper and a skin layer arranged on an upper surface of the metal layer and including copper and nickel, may be provided.

Abstract: A storage device, including: a nonvolatile memory device including a plurality of memory cells; and a controller configured to perform a write operation on at least one write unit included in the plurality of memory cells, and to perform an erase operation on at least one erase unit included in the plurality of memory cells, wherein the controller is further configured to: allocate a plurality of zones to a storage space of the nonvolatile memory device in response to a request of an external host device, select two or more erase units among a plurality of erase units of the plurality of memory cells to be allocated to each of the plurality of zones based on a zone map table, fixedly and sequentially manage logical addresses of data written in the plurality of zones, wherein the controller includes an internal buffer configured to store first data to be written in a first zone from among the plurality of zones, and wherein the controller is further configured to perform a backup operation for the first data b

Abstract: A cooking apparatus including: a chamber; a camera configured to photograph a cooking object placed in the chamber; and a controller to be electrically connected to the camera, the controller configured to: control the camera to acquire a plurality of image frames of the cooking object while cooking is being performed; identify a change in a state of the cooking object in the chamber from the acquired plurality of image frames; extract a portion of image frames among the acquired plurality of image frames based on the change in the state of the cooking object; and add a sound corresponding to the change in the state of the cooking object to the extracted portion of image frames to generate a summary video of a cooking process.

Abstract: Provided is an antenna module including a plurality of conductive layers stacked in a first direction, the antenna module including a first patch antenna including at least one radiator provided in at least one conductive layer, and an electromagnetic band gap (EBG) structure including a plurality of pillars spaced apart from the at least one radiator in a direction perpendicular to the first direction, the plurality of pillars surrounding the at least one radiator, wherein each of the plurality of pillars includes two or more plates provided parallel with each other in two or more conductive layers, respectively, and at least one via connecting the two or more plates.

Abstract: In a manufacturing method of a wafer, the method including: an operation of preparing a wafer including a semiconductor chip region and a test region, measuring a measurement region included in the test region with an atomic force microscope (AFM), the measurement region including a plurality of metal lines having a constant line width and a constant pitch; determining a surface roughness value of the test region based on a result of the measuring of the measurement region; determining a step difference value of the metal lines of the test region based on the surface roughness value; and determining a step difference value of bonding pads in the semiconductor chip region based on the step difference value of the metal lines.

Abstract: A semiconductor device fabrication apparatus including a grinder comprising a grinding part, the grinding part configured to grind a first surface of a substrate, a laser emitter configured to emit a femtosecond pulse laser to the first surface of the substrate transferred from the grinder, and a mount configured to attach a die attach film to the first surface of the substrate transferred from the laser emitter, wherein the grinding part is configured to grind the first surface of the substrate, which has been introduced into the grinder, and the laser emitter is configured to emit the femtosecond pulse laser to the ground first surface of the substrate may be provided.

Abstract: A semiconductor device may include a bit line on a substrate, a gate electrode over the bit line and spaced apart from the bit line, a gate insulation pattern on a sidewall of the gate electrode, a channel on a sidewall of the gate insulation pattern and including an oxide semiconductor material, a conductive pattern contacting an upper surface of the channel and including an amorphous oxide semiconductor material, and a contact plug contacting an upper surface of the conductive pattern. The contact plug may include a metal. The amorphous oxide semiconductor material may include fluorine (F), chlorine (Cl), nitrogen (N), hydrogen (H), or argon (Ar).

Abstract: Provided are an image sensor package with improved reliability and a method of fabricating the same. The image sensor package includes: a package substrate; an image sensor chip provided on the package substrate, and including a pixel area and a peripheral area surrounding the pixel area; a dam in the peripheral area, the dam having a rectangular ring shape and surrounding the pixel area; a transparent cover provided on the dam and covering an upper portion of the image sensor chip; and a sealing material sealing the image sensor chip and covering side surfaces of the transparent cover. The dam includes a stress relaxation layer (SRL) and a body layer on the SRL, and the SRL has a lower viscosity than a viscosity of the body layer.

Abstract: An operating method of a calibration system for a display device obtains image information about an image displayed on display device and wavelength information about pixels of the image information using a hyperspectral camera included in an electronic device, transmits the obtained image information and wavelength information to a first application in the electronic device, generates calibration data about the obtained image information and wavelength information through the first application and transmits the calibration data to a second application in the display device, and performs color calibration of the display device based on the calibration data transmitted to the second application to display a color calibrated image.

Abstract: A semiconductor package including a substrate comprising a plurality of vias; a chip stack on the substrate; and a mold layer on the substrate and on at least a portion of the chip stack. The chip stack includes a first semiconductor chip; second semiconductor chips stacked on the first semiconductor chip; a third semiconductor chip on the uppermost one of the second semiconductor chips; and non-conductive layers between the first semiconductor chip and the second semiconductor chips. A first chip pad of the first semiconductor chip is bonded to a substrate pad of the substrate. A second chip pad of the uppermost one of the second semiconductor chips is bonded to a third chip pad of the third semiconductor chip. Each of the second semiconductor chips is electrically connected to another of the second semiconductor chips or the first semiconductor chip.