Abstract: A magnetic memory device includes a substrate including a cell region and a peripheral circuit region, lower contact plugs on the cell region, data storage structures on the lower contact plugs, and a peripheral interconnection structure on the peripheral circuit region. The peripheral interconnection structure includes a line portion extending in a direction parallel to a top surface of the substrate, and contact portions extending from the line portion toward the substrate. A height of each of the contact portions is less than a height of each of the lower contact plugs.

Abstract: An electronic apparatus including a coupler attachable to and detachable from a support which is to support the electronic apparatus, the coupler being arrangeable on a rear surface of the electronic apparatus, a memory to store at least one instruction, and a processor configured to execute the at least one instruction stored in the memory to control a current applied to a magnetic energy control magnet included in one of the coupler and the support such that the coupler is attached to or detached from the support.

Abstract: A display device includes: a charge sharing controller to generate the plurality of group switch control signals based on first bits of (K?1)th digital data groups and second bits of digital data groups. The (K?1)th digital data groups correspond to pixel values of a (K?1)th row of the display panel. The Kth data digital groups correspond to pixel values of a Kth row of the display panel. The charge sharing controller is configured to, with respect to each of the plurality of source line groups, activate each of the plurality of group switch control signals to perform the charge sharing in response to the first bits satisfying a first condition, and the first bits and the second bits satisfying a second condition. The first bits and the second bits are not compared to each other to output a count value.

Abstract: Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

Abstract: Provided is a semiconductor device including an active pattern extended in a first direction, a plurality of gate structures including a gate electrode and a gate spacer disposed to be spaced apart from each other in the first direction on the active pattern and extended in a second direction, a source/drain pattern on the active pattern, a source/drain contact on the source/drain pattern, and a contact liner structure extended along a sidewall of the source/drain contact, being in contact with the sidewall of the source/drain contact. The contact liner structure includes a first contact liner and a second contact liner on the first contact liner. The first contact liner includes a first bottom portion, and a first vertical portion protruded from the first bottom portion and extended in a third direction. A lower surface of the contact liner structure is higher than an upper surface of the source/drain pattern.

Abstract: In a method of recovering a bootloader in a mobile electronic device, a bootloader recovery signal is transmitted from a bridge board to the mobile electronic device. The bridge board includes a first internal path and a second internal path. The mobile electronic device includes a third internal path and a fourth internal path. The bootloader recovery request signal is transmitted based on the first internal path and the third internal path. a boot mode of the mobile electronic device is changed based on the first internal path and the fourth internal path in response to receiving the bootloader recovery request signal. Bootloader recovery data is transmitted from a host device to the bridge board based on the changed boot mode. The bootloader recovery data is transmitted from the bridge board to the mobile electronic device based on the second internal path and the third internal path.

Abstract: Provided is a system for distributed processing of data that includes a data storage storing raw data generated in a fabrication process in real time; a database storing information associated with each of the raw data in real time; a master service that monitors the database on the basis of the information, selects processing targets to be processed among the raw data, and stores metadata associated with the processing targets in a queue; and a plurality of pods which make requests for jobs to the master service, receive metadata from the master service, access the raw data stored in the data storage using the received metadata, and perform the jobs on the raw data.

Abstract: Provided are a method of performing a convolution operation between a kernel and an input feature map based on reuse of the input feature map, and a neural network apparatus using the method. The neural network apparatus generates output values of an operation between each of weights of a kernel and an input feature map, and generates an output feature map by accumulating the output values at positions in the output feature map that are set based on positions of the weights in the kernel.

Abstract: Image processor circuitry includes a memory storing a program of instructions, and processing circuitry configured to execute the program of instructions to receive input data from an image sensor and detect an operation mode of the image sensor based on the input data, provide configuration data determined in association with the operation mode of the image sensor, and process image data in the input data in accordance with the operation mode and the configuration data.

Abstract: A testing method, device and/or system based on a Soft Subscriber Identity Module (SoftSIM) are provided. The testing method based on a SoftSIM including receiving a SoftSIM and a testing traffic value transmitted by a SoftSIM cloud server, importing and activating the received SoftSIM and completing registration in a network, and performing a real-network testing based on the SoftSIM and the received testing traffic value may be provided. According to the testing method, automatic real-network testing of a production line can be achieved by using limited SoftSIM resources and traffic to avoid frequent insertion of physical SIM cards on the production line, and the cost of a large number of physical SIM cards is saved and testing is facilitated by using flexible SoftSIM configurations. The use of dynamically configurable SoftSIM communication avoids wasting the communication cost of individual physical SIM cards.

Abstract: A semiconductor package including a dielectric layer on a substrate and having an opening that partially exposes a top surface of the substrate, a capacitor chip on the substrate and in the opening of the dielectric layer, connection terminals between the substrate and the capacitor chip and connecting the substrate and the capacitor chip to each other, dielectric patches on the substrate and in the opening of the dielectric layer, and an under-fill filling a space between the substrate and the capacitor chip may be provided. The space between the substrate and the capacitor chip includes a first region, a second region, and a third region between the first and second regions. The connection terminals are on the first region and the second region. The dielectric patches are on the third region.

Abstract: A semiconductor device includes a first chip structure including a wiring structure disposed on a circuit elements, and first bonding metal layers and a first bonding insulating layer on the wiring structure, an upper surface of the first chip structure having an edge region and an inner region surrounded by the edge region, a second chip structure disposed on an inner region of the upper surface of the first chip structure, and including second bonding metal layers respectively bonded to the first bonding metal layers, a second bonding insulating layer bonded to the first bonding insulating layer, and a memory cell layer on the second bonding metal layers and the second bonding insulating layer, an insulating capping layer disposed on an upper surface of the second chip structure and extending to the edge region, and a connection pad disposed on a region of the insulating capping layer.

Abstract: A semiconductor device is provided.

Abstract: An integrated circuit (IC) device including fin-type active regions parallel to each other on a substrate, the fin-type active regions extending in a first lateral direction, a first nanosheet stack apart from a fin top surface of a first fin-type active region selected from the fin-type active regions, the first nanosheet stack including at least one nanosheet facing the fin top surface of the first fin-type active region, a gate structure surrounding the first nanosheet stack, the gate structure extending in a second lateral direction, a first source/drain region in contact with one sidewall of the first nanosheet stack, and a second source/drain region in contact with another sidewall of the first nanosheet stack , wherein a greatest width of the first source/drain region is less than a greatest width of the second source/drain region in the second lateral direction may be provided.

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region extending in a first direction on a substrate, a plurality of channel layers spaced apart from each other in a vertical direction, a gate structure enclosing the plurality of channel layers, respectively, and a source/drain region contacting the plurality of channel layers. The source/drain region includes a first epitaxial layer extending to contact the plurality of channel layers, and a second epitaxial layer on the first epitaxial layer. A surface in which the first epitaxial layer and the second epitaxial layer contact each other includes: first surfaces having a first slope; second surfaces having a second slope, different from the first slope; first bent portions between the first surfaces and the second surfaces; and a second bent portion in which the second surfaces meet.

Abstract: An electronic device comprises: a memory to store an image input; a backlight unit; a driving unit to output a driving current to the backlight unit; and a processor to identify, based on a grayscale value of the image, a first intensity of the driving current corresponding to one from among a plurality of time sections of a backlight dimming section, obtaining, based on the identified first intensity, a first control value that allows control of an intensity of the driving current, providing a second control value, which is greater than a first control value to the driving unit, that allows the driving unit to output a driving current of a second intensity that is greater than the first intensity, and provide the first control value to the driving unit that allows the driving unit to output the driving current of the first intensity during the one time section.

Abstract: A memory device includes a plurality of gate electrodes spaced apart from each other in a first direction, a memory layer comprising a plurality of memory regions that protrude and extend in a second direction perpendicular to the first direction to face the plurality of gate electrodes, respectively, a plurality of first insulating layers extended to spaces between the plurality of memory regions between the plurality of gate electrodes, a channel layer disposed between the memory layer and the plurality of gate electrodes, the channel layer having a shape including a plurality of first regions surrounding the plurality of memory regions and a second region that connects the plurality of first regions to each other in the first direction, and a gate insulating layer arranged between the channel layer and the plurality of gate electrodes.

Abstract: A method of personalized image retrieval includes obtaining a natural language query including a name; replacing the name in the natural language query with a generic term to provide an anonymized query and named entity information; obtaining a plurality of initial ranking scores and a plurality of attention weights corresponding to a plurality of images using a trained scoring model that inputs the anonymized query and the plurality of images; obtaining a plurality of delta scores corresponding to the plurality of images using a re-scoring model that inputs the plurality of attention weights and the named entity information; and obtaining a plurality of final ranking scores by modifying the plurality of initial ranking scores based on the plurality of delta scores. The trained scoring model performs semantic based searching and the re-scoring model determines a probability that faces detected in the plurality of images correspond to the name.

Abstract: A row decoder circuit includes a first transistor connected to a power supply node and a first node; a plurality of second nodes connected in parallel between the first node and a power ground node, each of the plurality of second nodes being connected to a corresponding word line among the plurality of word lines; a plurality of second transistors connected between the first node and the plurality of second nodes; a plurality of third transistors connected between the plurality of second nodes and a power ground node; a comparator outputting a detection signal by receiving a voltage of the first node and a reference voltage. In a pre-charging period, the first transistor is turned on, the plurality of second transistors are turned on, and the third transistors are turned off, so that the first node and the plurality of second nodes are charged.

Abstract: A bit line sense amplifier includes a differential amplifier configured to receive an input signal from a bit line through an input terminal of the bit line sense amplifier and output a first signal to a first node of the bit line sense amplifier, a sensing inverter configured to receive the first signal and output a second signal to a second node of the bit line sense amplifier, the second signal resulting from inverting the first signal, a first switch configured to electrically connect the second node to a positive input of the differential amplifier, a second switch configured to electrically connect the first node to the positive input of the differential amplifier, and a third switch configured to electrically connect the second node to a negative input of the differential amplifier.