Abstract: Method and systems are provided for robust disparity estimation based on cost-volume attention. A method includes extracting first feature maps from left images captured by a first camera; extracting second feature maps from right images captured by a second camera; calculating a matching cost based on a comparison of the first and second feature maps to generate a cost volume; generating an attention-aware cost volume from the generated cost volume; and aggregating the attention-aware cost volume to generate an output disparity.

Abstract: An electronic device is provided. The electronic device includes a display, a communication circuit, a processor operatively connected to the display and the communication circuit, and a memory operatively connected to the processor. The memory stores instructions that, when executed, cause the processor to receive information about a time interval and user interface information, which are associated with a response to a user utterance input to a first external electronic device, from a second external electronic device through the communication circuit, to determine whether the display is in an active state within the time interval, and to provide a first user interface corresponding to the user interface information through the display based on the determination that the display is in the active state within the time interval.

Abstract: A semiconductor package includes a package substrate having a first insulating layer, a wiring layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and covering at least a portion of the wiring layer, a pair of support members disposed to face each other on the second insulating layer of the package substrate, and a pair of semiconductor chips disposed between the pair of support members and electrically connected to the wiring layer, wherein the second insulating layer has an opening surrounding at least a portion of each of the pair of semiconductor chips.

Abstract: In a method of writing data in a nonvolatile memory device, a write command, a write address and write data to be programmed are received. Offset information representing a verification level is received. The offset information is provided when the write data corresponds to a distribution deterioration pattern by checking an input/output (I/O) pattern of the write data. When the offset information is received, the write data is programmed based on the offset information such that at least one state among a plurality of states included in a distribution of threshold voltages of memory cells in which the write data is stored is changed.

Abstract: A semiconductor device includes a substrate including an active region in a first direction, a plurality of channel layers on the active region and disposed in a direction perpendicular to an upper surface of the substrate, a gate electrode respectively surrounding the plurality of channel layers, and a source/drain structure respectively disposed on both sides of the gate electrode in the first direction and connected to each of the plurality of channel layers. The gate electrode extends in a second direction crossing the first direction. The gate electrode includes an overlapped portion in a region of the gate electrode on an uppermost channel layer of the plurality of channel layers. The overlapped portion of the gate electrode overlaps the source/drain structure in the first direction and has a side surface inclined toward the upper surface of the substrate.

Abstract: A flip-flop circuit includes a first master latch circuit transmitting an inverted signal of an input signal received from an external device to a first node and transmitting an inverted signal of a signal of the first node to a second node, according to a first control signal having a first logic level or a second control signal having a second logic level, a first slave latch circuit transmitting an inverted signal of a signal of the second node to a third node according to the first control signal having the second logic level or the second control signal having the first logic level, a first output inverter generating a first output signal by inverting a signal of the third node, and a first control signal generation circuit generating the first control signal and the second control signal based on a clock signal and the signal of the first node.

Abstract: In a method of color decomposition, inter-color images indicating similarity between color sensitivities are generated based on color images. Conversion coefficients of the color images and the inter-color images with respect to a white image are determined. A pseudo-white image corresponding to the color images and the inter-color images is generated using the conversion coefficients the pseudo-white image similar to a real white image is generated using the inter-color images indicating similarity between color sensitivities. Deep learning of the artificial neural network is performed efficiently using the color images and the pseudo-white image and the demosaiced images of high quality are generated using the trained artificial neural network that is trained.

Abstract: A method of operating a storage device including a non-volatile memory and a multi-core processor with at least two cores includes the following steps: receiving, by a host interface of the storage device, a first command from a host for requesting the non-volatile memory to perform a predetermined memory operation; generating, by a task scheduler of the storage device, first and second tasks from the first memory command; selecting, by the task scheduler, a first core from among the at least two cores based on execution times of the at least two cores; assigning, by the task scheduler, the first and second tasks to the first core; and requesting, by the first core, a subsequent task from the scheduler while the first core processes the first assigned task and loads code for processing the second task.

Abstract: An electronic device is disclosed. The electronic device of the disclosure comprises: a memory in which a learned artificial intelligence model is stored; and a processor for inputting an input image to the artificial intelligence model and outputting an enlarged image with increased resolution, wherein the learned artificial intelligence model includes an upscaling module for acquiring the pixel values of interpolated pixels around a cell according to a function having a nonlinearly decreasing symmetric form with reference to an original pixel in the enlarged image, the original pixel corresponding to a pixel of the input image.

Abstract: A controller is provided. The controller creates a page table including page table entries including mapping information for translating a virtual address to a physical address. Each of the page table entries includes: a virtual page number, a physical frame number, valid information, and size information. The virtual page number is included in a virtual address, the physical frame number is included in a physical address, the valid information includes a first predetermined number of bits, and the size information includes a second predetermined number of bits. The first predetermined number of bits represents an address translation range in a page table entry or a number of page table entries to be grouped, and the size information represents a size indicated by each bit of the first predetermined number of bits.

Abstract: An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom patterned semiconductor layers may be separated from each other by an interlayer insulating layer that may include metal interconnections for conducting signals between devices formed in the patterned semiconductor layers and from external devices.

Abstract: A method for performing key exchange for a security operation in a storage device includes generating, by a trusted third party (TTP), a first certificate based on a first user ID and first public key and generating a second certificate based on a second user ID and second public key. While the storage device is accessed by the first user ID, a first verification is performed on the second certificate based on a third certificate. When the first verification is successfully completed, a ciphering key is derived based on a first private key and the second public key. While the storage device is accessed by the second user ID, a second verification is performed on the first certificate based on the third certificate. When the second verification is successfully completed, the ciphering key is derived based on a second private key and the first public key.

Abstract: A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.

Abstract: Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp2 bonding structure.

Abstract: A semiconductor package comprising a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes a first semiconductor body, an upper pad structure, and a first through-electrode penetrating the first semiconductor body and electrically connected to the upper pad structure, and the second semiconductor chip includes a second semiconductor body, a lower bonding pad, and an internal circuit structure including a circuit element, internal circuit wirings, and a connection pad pattern disposed on the same level as the lower bonding pad, the upper pad structure includes upper bonding pads and connection wirings, the upper bonding pads are disposed at positions corresponding to the lower bonding pad and the connection pad pattern, and the internal circuit structure is electrically connected to the first through-electrode through at least one of the upper bonding pads and the connection wirings.

Abstract: An electronic apparatus is disclosed. The electronic apparatus includes a memory storing at least one instruction, and a processor, electrically connected to the memory, configured to, by executing the instruction, obtain, from an input image, a noise map corresponding to the input image; provide the input image to an input layer of a learning network model including a plurality of layers, the learning network model being an artificial intelligence (AI) model that is obtained by learning, through an AI algorithm, a relationship between a plurality of sample images, a respective noise map of each of the plurality of sample images, and an original image corresponding to the plurality of sample images; provide the noise map to at least one intermediate layer among the plurality of layers; and obtain an output image based on a result from providing the input image and the noise map to the learning network model.

Abstract: A method and electronic device for updating a leakage response for leakage cancelation. The electronic device includes a radar transceiver, a memory, and a processor. The processor is configured to determine whether an object is within proximity of and within a field of view of the radar transceiver, obtain a leakage measurement for the radar transceiver in response to determining that no object is proximate to and within the field of view of the radar transceiver, and update the leakage response for leakage cancelation based on the leakage measurement.

Abstract: An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

Abstract: An access method of a nonvolatile memory device included in a user device includes receiving a write request to write data into the nonvolatile memory device; detecting an application issuing the write request, a user context, a queue size of a write buffer, an attribute of the write-requested data, or an operation mode of the user device; and deciding one of a plurality of write modes to use for writing the write-requested data into the nonvolatile memory device according to the detected information. The write modes have different program voltages and verify voltage sets.