Abstract: A memory device includes a first semiconductor layer and a second semiconductor layer disposed with respect to the first semiconductor layer in a third direction. The first semiconductor layer includes a memory cell array, a bitline and a complementary bitline coupled with the memory cell array, a first vertical wire coupled with the bitline, and a second vertical wire coupled with the complementary bitline. The second semiconductor layer includes a peripheral circuit, a bitline sense amplifier, first and second control lines coupled with the bitline sense amplifier, a third vertical wire coupled with the bitline sense amplifier, and a fourth vertical wire coupled with the bitline sense amplifier. The bitline sense amplifier includes at least one first transistor pair that is shared by at least one of the first and second control lines.

Abstract: A layout design method includes receiving input data defining a semiconductor integrated circuit, performing an arrangement operation and a routing operation based on the input data to obtain a first layout of the semiconductor integrated circuit including plural blocks, setting, on the first layout, a first switch area in which first switches are to be arranged, and arranging the first switches in the first switch area, and arranging second switches in a second switch area that is different from the first switch area to obtain a second layout of the semiconductor integrated circuit.

Abstract: A washing machine may include a drum, a driving device to rotate the drum, a control panel to receive input of a washing course and information indicating a reservation ending time, a memory to store information on time for proceeding with a washing course corresponding to an operation mode of a plurality of operation modes, and at least one processor configured to: obtain a target heating temperature lower than a set temperature of the washing course according to a general mode of the plurality of operating modes, based on a remaining time, being longer than a time to be spent in the general mode according to the stored information on time for proceeding with the washing course in the general mode, and control the driving device to proceed with the washing course in an operation mode of the plurality of operation modes based on the obtained target heating temperature.

Abstract: A processor-implemented method includes receiving a mapping instruction to map target data onto a process address space, in response to reception of the mapping instruction, marking an unused node in a tree that manages the process address space as a use node to reuse, and mapping the target data onto a virtual area in the process address space, wherein the tree manages the virtual area onto which the target data is mapped as the use node.

Abstract: A semiconductor package may include a first semiconductor chip, a second semiconductor chip spaced apart from the first semiconductor chip, an adhesive layer including an interposition portion and a side portion, and a molding layer. The molding layer may surround the first semiconductor chip, the second semiconductor chip, and the adhesive layer. The interposition portion may be between the first and second semiconductor chips. The side portion may contact a side surface of the first semiconductor chip and a side surface of the second semiconductor chip. A top surface of the side portion is curved, and an outer side surface of the side portion is flat.

Abstract: According to various embodiments, an electronic device may include at least one housing including a rear cover, a conductive structure disposed in an inner space of the at least one housing, and a first antenna structure in the inner space, the first antenna structure including a substrate including a first substrate surface and a second substrate surface facing in an opposite direction to the first substrate surface; and a plurality of antenna elements disposed on the substrate. The plurality of antenna elements are configured to transmit signals in a direction towards the conductive structure. The first antenna structure may be disposed such that the first substrate surface faces in a first direction so as to face the conductive structure. The conductive structure is configured to change direction of the signals transmitted by the plurality of antenna elements to form a beam pattern through the rear cover.

Abstract: An image sensor device includes a digital pixel that includes a photo detector, a comparator, and a memory circuit, a pixel driver that controls the digital pixel, and a digital logic circuit that performs a digital signal processing operation on a digital signal output from the digital pixel. The photo detector and a first portion of the comparator are formed in a first semiconductor die, a second portion of the comparator, the memory circuit, and the pixel driver are formed in a second semiconductor die under the first semiconductor die, and the digital logic circuit is formed in a third semiconductor die under the second semiconductor die.

Abstract: A method and apparatus for training a short circuit detection model are disclosed. The method includes generating virtual battery models with different battery parameter sets, based on battery data measured by a real battery in a non-short circuit state, by applying a constraint corresponding to a short circuit state to the virtual battery models, generating a virtual test result of the short circuit state, and training a short circuit detection model configured to detect the short circuit state using the virtual test result.

Abstract: A semiconductor package may include: a wiring structure having a structure in which at least one insulating layer and at least one wiring layer are alternately stacked; a semiconductor chip disposed to vertically overlap the wiring structure; and a conductive shielding layer accommodating the semiconductor chip, and covering a portion of a side surface of the wiring structure to be connected to a ground of the at least one wiring layer, wherein the other portion of the side surface of the wiring structure may not be covered by the conductive shielding layer.

Abstract: An electronic device includes: a projector; a camera; one or more processors; and memory storing instructions that, when executed by the one or more processors, cause the electronic device to: control the projector to display a projected image on a screen, wherein the screen includes surfaces; control the camera to obtain a captured image including the surfaces and the projected image; identify, based on the captured image, shapes of the surfaces and areas of the projected image projected onto the surfaces; and correct the projected image, based on the shapes of the surfaces and the areas of the projected image, by transforming the projected image into one from among a three-dimensional image and a flat image.

Abstract: A memory device is provided. The memory device includes: a plurality of sub-array regions arranged spaced apart in a first and second horizontal directions, and each sub-array region including a plurality of memory cells, the first horizontal direction crossing the second horizontal direction; a dummy region disposed between the plurality of sub-array regions, the dummy region including a first metal pattern extending in the first horizontal direction at a first layer, a first lower contact extending in a vertical direction on a first portion of the first metal pattern, and a second lower contact extending in the vertical direction on a second portion of the first metal pattern; and a peripheral circuit region including a first upper contact connected to the first lower contact, a first circuit connected to the first upper contact, a second upper contact connected to the second lower contact, and a second circuit connected to the second upper contact.

Abstract: A display device for performing image processing by using a neural network including a plurality of layers, may obtain a plurality of pieces of model information respectively corresponding to pixels included in a first image based on object features respectively corresponding to the pixels; identify the plurality of pieces of model information respectively corresponding to the plurality of layers and the pixels input to the neural network based on information about a time point at which each of the pixels is processed in the neural network; update parameters of the plurality of layers, based on the plurality of pieces of model information; and obtain a second image by processing the first image via the plurality of layers to which the updated parameters are applied; and display the second image.

Abstract: An apparatus for dicing a wafer includes a stage configured to receive a wafer, and move the wafer in a first direction, and a plurality of laser heads above the stage along the first direction, and as the stage moves the wafer in the first direction, the plurality of laser heads are configured to emit a plurality of laser beams onto the wafer along a plurality of cutting lines, the plurality of cutting lines extending in the first direction and each cutting line spaced apart from other cutting lines in a second direction, the second direction perpendicular to the first direction.

Abstract: A method for manufacturing a semiconductor device is provided and includes: forming a stack structure on a substrate; forming a mask pattern on the stack structure; forming a trench inside the stack structure by performing an etching process, using a process gas, that etches a portion of the stack structure; and forming a protective film pattern on a sidewall and an upper surface of the mask pattern, wherein the process gas includes at least one from among MoF6, MoF4, AlF3 and MgF2, the protective film pattern includes a material different from a material of each of the mask pattern and the process gas, and a thickness of a portion of the protective film pattern formed on the upper surface of the mask pattern is greater than a thickness of a portion of the protective film pattern formed on the sidewall of the mask pattern.

Abstract: A storage device is provided. The storage device includes: a nonvolatile memory device; and a controller configured to: receive first data from the nonvolatile memory device; perform first error correction decoding with respect to the first data to obtain second data; control an error correction capability and an error detection capability of second error correction decoding based on information about the first error correction decoding; and perform the second error correction decoding with respect to the second data based on the error correction capability and the error detection capability to obtain third data.

Abstract: A method performed by a head mounted display (HMD) device includes: determining a sleep onset preparation start time; and displaying, on a display, a sleep onset preparation screen to which a visual effect is applied, from the sleep onset preparation start time, in a stepwise manner during a sleep onset preparation time interval, where the visual effect that is applied in the stepwise manner comprises a visual effect of switching a virtual screen output through an entire display area of the display to a video see through (VST) screen, where the VST screen displays the virtual screen with a non-virtual screen as a background in the entire display area of the display, where the non-virtual screen is based on an image captured through a front camera, and where the virtual screen is based on content executed by the HMD device.

Abstract: A semiconductor device may include a substrate containing first to third doping regions, first and second gate structures between the first and second doping regions, and a gate separation layer between the first and second gate structures. Each of the first and second gate structures may include a first gate dielectric layer, a first gate conductive layer on the first gate dielectric layer, and a second gate conductive layer between the gate separation layer and the first gate conductive layer. The gate separation layer may include a first sidewall in contact with the first gate structure and a second sidewall in contact with the second gate structure. A top surface of the gate separation layer may be at a same level as a top surface of the second gate conductive layer.

Abstract: A semiconductor package includes a substrate including: a substrate comprising a through-hole; a first semiconductor chip in the through-hole; an adhesive layer on a side surface of the first semiconductor chip in the through-hole; a first redistribution structure on an upper surface of the substrate and bonded and connected to the substrate; a second redistribution structure on a lower surface of the substrate and bonded and connected to the substrate; a second semiconductor chip on the first redistribution structure; and a through-via spaced apart from the first semiconductor chip in a horizontal direction and passing through the substrate in a vertical direction.

Abstract: A semiconductor package includes a first semiconductor chip including a plurality of upper pads, a non-conductive support layer on a top surface of the first semiconductor chip and including a plurality of openings, a second semiconductor chip on the first semiconductor chip and including a plurality of lower pads, a plurality of chip connecting terminals extending between the plurality of upper pads and the plurality of lower pads, and an insulation adhesive layer between the first semiconductor chip and the second semiconductor chip and at least partially covering the plurality of chip connecting terminals and the non-conductive support layer. A top surface of the non-conductive support layer is disposed closer to a bottom surface of the second semiconductor chip than top surfaces of the plurality of upper pads are disposed to the bottom surface of the second semiconductor chip.

Abstract: A semiconductor package includes a lower redistribution layer having a plurality of lower ball pads forming a plurality of lower ball pad groups, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, and an upper redistribution layer on the semiconductor chip and the expanded layer and having a plurality of upper ball pads forming a plurality of upper ball pad groups. The number of the plurality of upper ball pad groups may be the same as the number of the of the plurality lower ball pad groups. Each of the upper ball pads in one of the plurality of upper ball pad groups, from among the plurality of upper ball pads, may be a dummy ball pad.