Abstract: Methods and apparatus are described for receiving digital television signals where the receiver is capable of demodulating and demultiplexing the digital television signals from multiple, independent transmission channels. The preferred embodiment of the present invention provides for a Dual Channel Digital TV Receiver which receives signals from two independent transmission channels. In order to address each of the digital television signals from the two independent transmission channels, the Dual Channel Digital TV Receiver of the preferred embodiment of the present invention includes two independent paths for channel demodulation and transport stream demultiplexing. Thus, within the Dual Channel Digital TV Receiver of the preferred embodiment of the present invention, a signal from each of the transmission channels are received, decoded and sent for further processing or viewing, as desired by the user.

Abstract: A spindle motor assembly for a hard disk drive which has a fluid filled tube that dynamically balances the spindle motor. The assembly may include a hub which is rotated by an internal motor. A plurality of disks may be coupled to the hub and separated by a number of spacers. In one embodiment, the fluid filled tube is attached to the hub. In another embodiment, the fluid filled tube is attached to the spacer. The fluid within the tube is allowed to move during rotation of the hub. Movement of the fluid may dynamically balance the spindle motor.

Abstract: Zero detect of a difference of binary operands is disclosed. If the difference is zero, the bit-complement of the difference is a string of one's, and therefore incrementing the string of one's generates a carry-out bit of one. Likewise, if the difference is non-zero, the bit-complement of the difference will contain one or more zero's, and therefore incrementing the bit-complemented difference will generate a carry-out bit of zero. The operands include a minuend and M subtrahends. One embodiment includes providing a result representing a bit-complement of the difference, and then inspecting a carry-out bit generated by incrementing the result.

Abstract: A multiprocessor computer system includes a plurality of processors, called asymmetric processors, having mutually dissimilar control and data-handling characteristics. The asymmetric processors are controlled by a single operating system although the individual processors have instruction sets that are mutually independent of the other processors. The multiprocessor computer system uses a multiprocessor architectural definition of interrupt and exception handling in which a processor, called a data or vector processor, having a large machine state and a large data width detects exceptions but defers interrupt and exception handling operations to another processor, called a control processor, having a small machine state and data width. The small machine state and small data width of the control processor are well suited for executing operating system programs such as interrupt and exception handling since control programs typically involve monitoring and control of individual flags and pointers.

Abstract: A multiprocessor architectural definition provides that a program executing on a first processor interrupts a second processor by executing a software interrupt instruction. The software interrupt instruction includes an argument field for passing information from a program requesting the software interrupt. The argument, along with the opcode, is saved in a register designated for holding the argument. The information communicated via the argument is used in one embodiment to indicate a cause of the interrupt. In an embodiment, the information communicated via the argument designates an interrupt service routine to be activated in the interrupted processor.

Abstract: A floating point subtraction is performed on a first and second floating point number to obtain an exponent result and a fraction result, the first floating point number has a first exponent and a first fraction and the second floating point number has a second exponent and a second fraction. A first adder determines an exponent difference between the first and second exponents and, concurrently with determining the exponent difference, a prediction circuit predicts a massive cancellation prediction and a second adder determines the difference between the first and second fraction and generates a massive cancellation fraction result. Then it is determined whether the massive cancellation result is valid and if so, the massive cancellation fraction result is selected as a basis for the fraction result. If not, a result from the no massive cancellation path is selected as the basis for the fraction result.

Abstract: Synchronization of MPEG audio and video presentations is attained by detecting a lack of synchrony between the data presentations and modifying the audio data stream based on the detected lack of synchrony. Synchrony of the MPEG audio and video presentations is monitored by tracking the amount of data transferred to audio and video interfaces over time. Synchronization of MPEG audio and video presentations is achieved in a system in which audio and video interfaces are controlled by separate and independent timing signal generators by tracking the amount of audio and video data output by the respective audio and video interfaces. The amount of audio and video data output by the interfaces is compared and, as a result of the comparison, the audio data stream is modified to restore synchrony. Alternatively, presentation of the video data stream is modified to achieve synchrony.

Abstract: An initial estimate of a reciprocal of a floating point number is generated in one addition having correct sign, exponent and up to five or more bits of precision in the fraction by subtracting the input floating point number from a constant. The constant is determined such that subtracting the floating point number from the constant results in bit complementing the most significant m bits (f.sub.0 . . . f.sub.m), 1.ltoreq.m.ltoreq.n, of the fractional part of the floating point number to provide 1.f.sub.0 . . . f.sub.m , negating the exponent E and subtracting 1, to provide an initial estimate of the exponent=-E-1, and including in the constant a correction factor to further improve the initial estimate.

Abstract: A four-buffer MPEG decoder is provided for decoding MPEG video frames. A four-buffer frame controller and control method manage the four frame buffers including decoding, displaying and discarding of I-frames, P-frames and B-frames so that video data decoding is accelerated. The four-buffer frame controller and control method frees one frame buffer when the frame buffer contains obsolete data, defined as data which is no longer useful for decoding additional frames and for which storage is not necessary for displaying pictures in a correct temporal order. One example of an obsolete frame is a B-frame that is displayed. Another example is a P-frame for I-frame which is no longer used for motion compensation and has been displayed.

Abstract: A multi-standard start code detector system receives an incoming compressed video bit stream. The compressed video bit stream includes start codes interspersed between variable length bit streams. Assuming error-free useful data, zero stuffing bits preceding a next start code are rapidly discarded on a bit group-wise basis. A group of current bits are processed by comparing them to a start code feature pattern. If a match is not detected, the entire group of bits is concurrently replaced by a next group. However, because the zero stuffing bits are of variable length, the exact position of the start code pattern is unknown. Preceding each replacement operation, the next group of bits is processed to predetect a start code feature. Upon predetecting a start code feature, the replacement operation is modified to ensure that a group of current data bits will include the start code feature pattern. This allows the number of searched for patterns to be reduced and streamlines the comparison operation.

Abstract: A centroid-based object contour encoding method and device for encoding still images and moving pictures by rendering a more accurate contour representation with increased compression. The method includes the determination of a centroid and incrementing angle, the determination of distances between the centroid and boundary pixels on an object, and the encoding of the information determined. For moving pictures, the difference between the data of a current frame and the data of a previous frame are encoded by discrete cosine transforming and variable-length coding of the difference data.

Abstract: A cache control unit and a method of controlling a cache. The cache is coupled to a cache accessing device. A first cache request is received from the device. A request identification information is assigned to the first cache request and provided to the requesting device. The first cache request may begin to be processed. A second cache request is received from the cache accessing device. The second cache request is assigned to the first cache request and provided to the requesting device. The first and second cache requests are finally fully serviced.

Abstract: An initial estimate of a reciprocal of a square root of a floating point number is generated by subtracting the input floating point number from a constant and shifting the results to the right by one bit. Additionally, the initial estimate of a reciprocal of a square root of a floating point number can be determined by decrementing the exponent by one, shifting the exponent and fraction to the right by one bit, and subtracting the result from predetermined constant. The estimate for the reciprocal square root can also be determined by shifting the floating point number to the right by one bit and subtracting the shift result from a predetermined number to generate the initial estimate.

Abstract: The absolute difference of two signed or unsigned integer numbers (A, B) is calculated in one instruction cycle by bit-complementing the B operand, summing the A and bit-complemented B operands to obtain an intermediate result, detecting whether the intermediate result overflows, then either incrementing the intermediate result or bit-complementing the intermediate result as appropriate. The B operand is bit-complemented by a first inverter circuit (302). The A and bit-complemented B operands are summed in an adder (304) that provides a sum and sum-plus-one output. The sum output is bit-complemented by a second inverter circuit (306). A multiplexer (310) under the control of a control circuit (308) selects one of the bit-complemented sum output and sum-plus-one output, based on inspection of the most significant bits of the A operand, B operand, and sum output, a carry-out bit from the sum output, and a mode signal indicative of whether the operands are signed or unsigned values.

Abstract: A group of incoming data stream bits having packed variable length code ("VLC") words is applied to an entropy code bit length searching module. The group of bits is replicated within a plurality of matching modules selectively distributed among entropy code bit length searching logic units. Each unit of entropy code bit length searching logic supports a VLC word table as characterized by, for example, standard compression formats such as MPEG-1, MPEG-2, H.261, and H.263. The matching modules are divided into groups within the entropy code bit length searching logic units. A group of matching modules is allocated to each VLC bit length represented in the associated VLC word supported table. A number of matching modules are allocated to each bit length equal to a minimum number of patterns unique to VLC words of a particular bit length. The matching modules compare an incoming data group to respective patterns. A detected match is indicated by an appropriately set group output signal.

Abstract: An integrated circuit includes a test port operating at a first clock speed and at least one functional logic block operating at a second clock speed which is faster than the first clock speed. A control register, formed by boundary scan cells, operates at the first clock speed and provides control inputs to the functional block to control emulation tasks. The control register is writable via a serial shift operation through the test port while the functional block is operating. The outputs of the control register which are being provided to the functional block are held constant during the serial shift operation. An observation register, formed by boundary scan cells, operates at the first clock speed, and is readable through the test port via a serial shift operation, while the functional block is operating. The observation register receives signals from the functional block indicating status of the functional block.

Abstract: A floating point multiply-and-accumulate unit that performs an operation A*B.+-.C also determines an exponent difference (Ea+Eb)-Ec where Ea, Eb, and Ec are the exponents of values A, B, and C. The exponent difference indicates a class for the operation. In a first class, C is much greater than A*B and accumulation of a mantissa Mc of C with a mantissa Ma*Mb of A*B leaves mantissa Mc. In second and third classes, C and A*B are comparable and mantissas Mc and Ma*Mb overlap during accumulation. In a fourth class, A*B is much greater than C so that accumulation of mantissas Mc and Ma*Mb leaves Ma*Mb. The classes controls shift logic for alignment before accumulation or postnormalization after accumulation. For the first class, alignment or normalization are fixed according to Mc. For the second and third class, a fixed shift for alignment or normalization according to Ma*Mb is performed followed by a variable shift as indicated either by the exponent difference or cancellation detected during accumulation.

Abstract: An entropy code look up table processes incoming data and provides an n-bit output signal having an entropy code word and a bit.sub.-- length output signal. Entropy code words are successively packed without spacing bits into two sixteen-bit latches. An arithmetic unit keeps track of accumulated sizes of packed, unconveyed entropy code words. The n-bit output signal is converted into a thirty-two bit signal with spacing bits on either side of a current entropy code word. Using the accumulated size information, flow through multiplexer units insert spacing bits in bit positions corresponding to bit positions currently occupied by packed entropy code words. Any remaining bits in the thirty-two bit output signal are preferably set to logical zeros. With the current entropy code word properly aligned in the thirty-two bit output signal, a path selection logic unit utilizes the accumulated size information and a unary decoder to form a sixteen bit output signal.

Abstract: A method and apparatus for left-shifting a signed or unsigned integer operand and providing a clamped integer result in a single instruction cycle is disclosed. The apparatus includes a left-shifter for left-shifting the operand to obtain a shifted intermediate result and shifted-out bits. The apparatus also includes an overflow detector for generating an overflow signal in response to a sign bit of the operand, a sign bit of the shifted intermediate result, the shifted-out bits, and a mode signal indicative of whether the operand is signed or unsigned. The overflow signal has a first logical value when overflow occurs, and a second logical value in the absence of overflow.

Abstract: An optical tape cassette and a player for using the cassette. The optical tape cassette includes a drum on which optical tape is wound and two tape reels for supplying and winding the tape. The cassette player includes a driver having two rotating members which can be connected to the drum and tape take-up reel for driving the drum and tape take-up reel, respectively, and an optical pickup for projecting a light beam onto the optical tape which is wound about the periphery of the drum, thereby realizing a simplified structure and easy handling for home use.