Abstract: A detector circuit includes: a squaring circuit configured to receive an output of a power amplifier of a radio transmitter and to produce an output current, the output of the power amplifier including: a desired tone; a local oscillator leakage tone; and an image tone, and the output current of the squaring circuit including: a direct current (DC) component including a function of the desired tone and an alternating current (AC) component; and a DC current absorber electrically connected to an output terminal of the squaring circuit, the DC current absorber being configured to filter out the DC component of the output current of the squaring circuit to produce a filtered output of the squaring circuit, the filtered output including the AC component including functions of the local oscillator leakage tone and the image tone.

Abstract: A silicon layer etchant composition and associated methods, the composition including about 1 wt % to about 20 wt % of an alkylammonium hydroxide; about 1 wt % to about 30 wt % of an amine compound; about 0.01 wt % to about 0.2 wt % of a nonionic surfactant including both a hydrophobic group and a hydrophilic group; and water, all wt % being based on a total weight of the silicon layer etchant composition.

Abstract: The semiconductor package including a first semiconductor package including a first semiconductor package substrate, and a first semiconductor chip on the first semiconductor package substrate, an interposer disposed on the first semiconductor package is provided. Interposer electrically connects the first semiconductor package with an external semiconductor package, and has first and second sides opposed to each other. The second side is located between the first side and the first semiconductor package substrate, a first recess is formed in the second side of the interposer. The first recess has side walls extended from the second side toward the first side of the interposer and an upper surface connected to the side walls and the upper surface of the first recess faces the first semiconductor chip and a via in the interposer. The via does not transmit an electrical signal between the first semiconductor package and the external semiconductor package.

Abstract: Methods and apparatus are described for a User Equipment (UE) with reduced processing capabilities (e.g., Machine Type Communication (MTC) UE) to transmit and receive signaling are provided. The Downlink Control Information (DCI) formats scheduling a transmission of a Physical Uplink Shared CHannel (PUSCH) or a reception of a Physical Downlink Shared CHannel (PDSCH) are designed and have a smaller size than respective DCI formats for conventional UEs. DCI formats scheduling PUSCHs to or PDSCHs for a group of MTC UEs are also designed and can have a same size as DCI formats scheduling PUSCH or PDSCH for an individual MTC UE.

Abstract: A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A <001> direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.

Abstract: A method for operating a device in a wireless communication system is provided. The method includes receiving a plurality of embedded subscriber identity module (eSIM) profiles, each eSIM profile being associated with at least one quality of service (QoS) feature, performing a primary mapping between the plurality of eSIM profiles and applications available on the device based on QoS requirements of the applications, and performing transfer of data belonging to the applications using the mapped eSIM profiles corresponding to the primary mapping.

Abstract: Disclosed is an electronic device. The electronic device may include a first modem supporting communication for a first cellular network, a second modem supporting communication for a second cellular network, a processor electrically coupled to the first modem and the second modem, and a memory electrically coupled to the processor and including instructions, and the instructions, when executed by the processor, may cause the processor to perform an operation associated with a radio interface layer (RIL) corresponding to both the first modem and the second modem, and to acquire control information generated by the second modem via a control path connecting the first modem and the RIL. Moreover, various embodiment found through the present disclosure are possible.

Abstract: A semiconductor device including a substrate; a first active pattern on the substrate and extending in a first direction, an upper portion of the first active pattern including a first channel pattern; first source/drain patterns in recesses in an upper portion of the first channel pattern; and a gate electrode on the first active pattern and extending in a second direction crossing the first direction, the gate electrode being on a top surface and on a side surface of the at least one first channel pattern, wherein each of the first source/drain patterns includes a first, second, and third semiconductor layer, which are sequentially provided in the recesses, each of the first channel pattern and the third semiconductor layers includes silicon-germanium (SiGe), and the first semiconductor layer has a germanium concentration higher than those of the first channel pattern and the second semiconductor layer.

Abstract: An electroluminescent device and including a first electrode and a second electrode facing each other; an emission layer disposed between the first electrode and the second electrode, wherein the emission layer includes a quantum dot and a first electron transporting material represented by Chemical Formula 1; a hole transport layer disposed between the emission layer and the first electrode; and an electron transport layer disposed between the emission layer and the second electrode: wherein, the definitions of groups and variables in Chemical Formula 1 are the same as described in the specification.

Abstract: An image decoding method includes: splitting a first block included in an image on the basis of at least one of a split type and a split direction of the first block to determine at least one second block from the first block; determining one of a prediction mode of the at least one second block and whether to split the at least one second block on the basis of at least one of a size and a shape of the determined at least one second block; obtaining a prediction block of a block included in the at least one second block on the basis of one of the determined prediction mode and whether to split the at least one second block; and restoring the block included in the at least one second block on the basis of the prediction block of the block included in the at least one second block. Here, the split type represents one of binary-split, tri-split, and quad-split.

Abstract: An electronic device is disclosed. The present electronic device comprises a display, a speaker, an input unit, and a processor for controlling the display so that an image signal inputted through the input unit is displayed, controlling the speaker so that an audio signal synchronized with the displayed image signal is outputted, and controlling the display so that caption information corresponding to the audio signal outputted during a preset previous time is displayed on the basis of the point of time when a user command is inputted.

Abstract: A standard cell comprises a first active region and a first power rail, the first active region and the first power rail disposed in a first MOS region; a second active region and a second power rail, the second active region and the second power rail disposed in a second MOS region; and a gate electrode extending to cross the first and second active regions and the first and second power rails in a first direction, wherein the first power rail is disposed closer to a boundary between the first MOS region and the second MOS region than to a first side of the first MOS region opposite the boundary, and wherein the second power rail is disposed closer to the boundary between the first MOS region and the second MOS region than to a first side of the second MOS region opposite the boundary.

Abstract: An optical filter includes a near-infrared absorbing layer including a first material, the first material being configured to absorb light in a first wavelength spectrum belonging to a near-infrared wavelength spectrum. The optical filter includes a compensation layer adjacent to the near-infrared absorbing layer, the compensation layer including a second material different from the first material. The optical filter includes a metamaterial structure spaced apart from the near-infrared absorbing layer via the compensation layer, the metamaterial structure being configured to absorb or reflect light in a second wavelength spectrum at least partially overlapped with the first wavelength spectrum.

Abstract: An interconnection structure includes a dielectric layer, and a wiring pattern in the dielectric layer. The wiring pattern includes a via body, a first pad body that vertically overlaps the via body, and a line body that extends from the first pad body. The via body, the first pad body, and the line body are integrally connected to each other, and a level of a bottom surface of the first pad body is lower than a level of a bottom surface of the line body.

Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

Abstract: A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

Abstract: An infrared absorber includes a compound represented by Chemical Formula 1. An infrared absorbing/blocking film, a photoelectric device, an organic sensor, and an electronic device may include the infrared absorber. In Chemical Formula 1, Ar, X1, X2, Y1, Y2, R1, R2, R11, R12, R13, and R14 are the same as defined in the detailed description.

Abstract: A semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings.

Abstract: A light-emitting device includes an emission array including a plurality of light-emitting elements and a partition wall. The emission array includes a first region and a second region adjacent to each other. The partition wall is configured to isolate the first region and the second region from each other, such that the partition wall at least partially defines the first region in the emission array. The first region is associated with a first emission factor and the second region is associated with a second emission factor, the second emission factor different from the first emission factor.

Abstract: An electronic device and a method for controlling an electronic device are provided. The electronic device according to the disclosure includes a communicator; and a processor configured to: receive information on a plurality of function and a voice command for executing the plurality of functions, and function environment information for executing the plurality of functions, through the communicator, determine whether or not the electronic device executes the plurality of functions based on environment information and the functional environment information of the electronic device, when a received user's voice corresponds to the voice command, and control the electronic device to perform an operation corresponding to the determination result.