Abstract: For a SRAM having a sense amplifier amplifying memory data and a read/write control circuit controlling operations of the sense amplifier, a data output buffer circuit is provided, which includes: a drive output node from which data output buffer provides output data; a first circuit providing a NOR function of an SAS signal from the sense amplifier and an output enable signal (OE) from the read/write control circuit; a second circuit providing a NOR function of an SAS signal from the sense amplifier and the output enable signal (OE) from the read/write control circuit; a third circuit eliminating noise produced by transition in the outputs of the first and second circuit and also enhancing a response time; a fourth circuit inverting the output of the first circuit; a fifth circuit inverting twice, sequentially, the output of the second circuit; and a sixth circuit responsive to the fourth and fifth circuit, alternatively providing, depending on the SAS and an SAS signal from the sense amplifier, one of three

Abstract: A power-on reset circuit. The reset circuit provides an automatic reset pulse immediately after power-up. The supply voltage is provided to the reset circuit. An RC filter with a variable time constant provides a "hump" waveform which is coupled to a waveform shaper. The waveform shaper converts the hump voltage output from the RC filter into a reset signal. Latching mechanisms are included to prevent refiring of the reset signal.

Abstract: The present invention implements a static inverter-type TTL/CMOS level translator. The present invention utilizes a pair of transistors to suppress hot electron effects. The transistor pair limits maximum VDS to VCC-VTN at the first and second gain stages. A pair of resistors serve as a virtual VCC modulator to minimize voltage variations, stabilizing the VIL/VIH trip point. The resistors also minimize standby current so that the translator of the present invention can be used in a low standby current environment. The translator of the present invention provides faster speed, wider process margins, better reliability and lower standby current than prior art translators.