Abstract: This invention provides a method for manufacturing a semiconductor device which prevents residues from remaining around an etching pattern of a poly-silicon by making the poly-silicon be gradiently etched out. An oxide barrier layer is deposited over a poly-silicon layer, and impurities are implanted through the oxide barrier layer, wherein the concentration difference of impurities makes the poly-silicon have a graded sidewalls, and the value of resistance is controlled by the quantity of impurities. After removing the oxide barrier layer the poly-silicon is selectively etched into a poly electrode having a graded sidewall. The thermal treatment of the poly electrode is carried out and a polysilicon for another electrode is deposited and etched out.

Abstract: The present invention relates to a level translator which translates TTL level signals to ECL level. The translating speed is enhanced by making the input circuit of the level translator which receives the TTL data signal composed of an emitter coupled pair such that the circuit does not act in saturation mode. Also, by designing the circuit to make current flow from the pull-up transistor of the TTL transfer through the resistance of the present invention when the TTL data is high level, and to make current flow through the pull-down transistor of the driving TTL circuit into the TTL to ECL level translator when low level, the present invention makes the time delay from the driving TTL circuit to the ECL receiving circuit very small.

Abstract: This invention is related to a method for fabricating a DRAM cell. This invention makes the capacitor electrode and the source of the transistor connect more easily using the lateral diffusion of another dopant having higher diffusivity and same impurity type, which is added to the first ion implantation for the first electrode of storage capacitor. According to this invention the storage capacitor electrode and the source of the transistor are connected successfully, and it is possible to reduce the resistance between the capacitor electrode and the drain of the transistor.

Abstract: Present invention relates to the fabrication method of the bipolar transistor which includes NPN transistor and field-plate lateral PNP transistor.The arsenic implanted polycrystalline silicon is used for the emitter electrode of NPN transistor to increase the current gain, and for the field-plate of the lateral PNP transistor to reduce the collector-emitter leakage current.Also, this polycrystalline silicon is used for the ion implanting mask for the extrinsic base of the NPN transistor and for the emitter, collector of the lateral PNP transistor simultaneously.Therefore, the extrinisc base of NPN transistor and the emitter, collector of the lateral PNP transistor are self-aligned by the polycrystalline silicon, and so one mask is saved by this method.

Abstract: A precharge system of the divided bit line types for a SRAM (Static Random Access Memory) reduces the active current consumption and bit line peak current by decreasing the number of bit lines to be precharged at any one time during a precharge cycle. For this, the system has a block selection signal generator that responds to certain column addresses with a block selection signal. A sub-block selection signal generator responds to certain addresses among the remaining column addresses with a sub-block selection signal. A precharge decoder responds to pulses from the pulse generator and the block selection signal with a block selection precharge signal. A divided bit line precharge decoder responds to the sub-block selection signal and block selection precharge signal with a pulse for precharging only a certain sub-block of a certain block of the array of memory cells of the SRAM.

Abstract: A junction-breakdown protection semiconductor device provides a well region which prevents the junction between a metal conductor and a diffused region from breakdown even under a high voltage or high current input. The junction-breakdown protection semiconductor device includes a metal conductor to which a high voltage is applied a semiconductor region of high impurity concentration having a conductivity type which is opposite to the conductivity type of the substrate is connected to the metal conductor through an opening in an insulating film. A second semiconductor region of the same conductivity type as the first semiconductor region is formed deeper in junction depth than the first semiconductor region under the opening in the insulator for ohmic connection on the surface of the first semiconductor region.

Abstract: A dual-slope waveform generation circuit without a DC path and with decreased layout area including a pull-up and pull-down resistor, a transmission gate and an inverter. An input signal IN is applied to the pull-up transistor, to each gates of MOS transistors M.sub.1, M.sub.2 composing of the inverter A, and to drains of MOS transistors M.sub.3, M.sub.4 composing of the transmission gate B. A common node in the inverter is connected to the gate of the N type MOS transistor in the transmission gate. The sources of the transistors M.sub.3, M.sub.4 are connected to the gate of the pull-down transistor. An output signal OUT is applied to the gate of the transistor M.sub.4 and the signal is fed back.

Abstract: A FM detection system using a phase locked loop (PPL 20) and including: a wave shaping comparator (7) for accepting a signal V.sub.CO2 from a voltage controlled oscillator (4) which is 90.degree. out of phase with a control signal V.sub.CO1 from the voltage controlled oscillator (4), the comparator reshaping the signal to a square wave; an in-lock detector (8) for accepting the square wave and a frequency modulated input signal (VFM) to provide a sum frequency and a difference frequency; a low-pass filter (9) cutting off the sum frequency component, and filtering out the difference frequency signal when the PLL (20) is unlocked; a comparator (10) for comparing the output of the low-pass filter (9) with a reference voltage (V.sub.

Abstract: Present invention relates to the fabrication method of the bipolar transistor.With this method the emitter of high-concentrated n-type is contacted closely to the extrinsic base of high-concentrated p-type.This structure is obtained by making the emitter of the bipolar transistor be self- aligned by the side wall under-cut of the nitride layer using double layers of the low temperature oxide and the nitride layer.

Abstract: A level shifter for an input/output bus in a CMOS dynamic RAM employs a first and second PMOS transistor. The first and second PMOS transistors are connected to and cut off a current flow between a pair of input/output lines and a pair of input/output sense amplifier input lines which are connected to input/output sense amplifiers. First and second inverters are included for each of the first and second PMOS transistors, each inverter has an input for receiving a signal for a selection of the input/output line pair and has a respective output which is connected to a corresponding gate and drain of the first and second PMOS transistors.

Abstract: A sense amplifier and high performance DRAM, in combination, has in the DRAM at least one row of memory cells, whereby the memory cells of the row may be arranged in respective columns with memory cells of other rows. Each of the memory cells has a transistor and a capacitor connected serially between one of bit lines successively along the row and a fixed voltage source. Word lines are respectively connected to gates of the transistors of the memory cells for activating the memory cell selectively according to row address. The sense amplifier has a cross-coupled bistable flip-flop connecting the bit lines to each other in the row. A latch transistor connected to the flip-flop detects and amplifies a voltage difference between the bit lines. The bit lines are equalized and precharged with a reference voltage in response to a clock control signal. A cross-coupled pair of transistors also connecting the bit lines to each other transfer a charging voltage to the bit lines.

Abstract: This invention is related to an integrated driving circuit which can control high voltage and power, and more particularly to a high voltage and power driving circuit by employing BiCMOS technology. The principal object of this invention is to provide an integrated high voltage and high power driving circuit which is reliable by using BiCMOS technology without external discrete components.

Abstract: This invention provides a method for fabricating a BiCMOS device, in which said device has a Si substrate of a first conductivity in which there is formed a first substrate region of a second conductivity for a bipolar transistor, a second substrate region of said second conductivity for a first MOSFET, having a source and drain of the first conductivity, and in which a part of said Si substrate is formed to provide a second MOSFET which has a source and drain of the second conductivity. A first nitride layer is used to prevent the substrate under a masking layer from oxidizing during the following oxidation processes, wherein the masking layer is composed of a oxide layer and the nitride layer. After some processes, the masking layer is removed. Implanting As impurities, a new oxide layer and a new nitride layer are deposited, wherein the role of the nitride layer is to protect a shallow emitter region.

Abstract: A C-MOS address buffer for use in a semiconductor memory device is clocked by an inverted column address strobe signal .phi..sub.CAL of an external column address strobe signal CAS. The signal .phi..sub.CAL is supplied to the drain of a feedback transistor in a schmitt trigger and is reinverted to provide a signal corresponding to the address strobe signal CAS. This signal is coupled to the gate of a transistor which controls the application of a supply voltage to the schmitt trigger circuit. Invalid timing address signals between the address input signal Ai and the clock signal comprising the signal .phi..sub.CAL are thus prevented. Also sufficient address set up time and hold time are guaranteed.

Abstract: A normal decoder and a redundant decoder having address program devices are used for the replacement of bad cells. The number of address program devices is one more than the number of input address bits for selecting a normal row or column. The input signals of the additional program device are complementary to the input signals of one of the other program devices. The program of the program devices have two steps to repair the faulty cells. To increase the reliability of redundancy, a nonvolatile memory element used in the program devices is a bridge connected four cell FLOTOX type nonvolatile memory device.

Abstract: A data transmission circuit for CMOS dynamic random access memory devices having a data input buffer for converting TTL input data signals to CMOS logic level data signals and providing true and complement data signals on a pair of data bus lines, a pair of transmission gates for transmitting the true and complement data signals to a pair of true and complement I/O bus lines comprising a pair of similar constitutional I/O bus line pull-up or pull-down circuits between the output lines of the transmission gates and the I/O bus lines for making logic operations on the data bus lines. The I/O bus lines alternate at the time of a writing operation and a I/O bus line equalizing circuit is connected between the true and complement I/O bus lines for equalizing the pair of the I/O bus lines at a high speed, before or after a writing cycle.

Abstract: The present invention relates to an integrated circuit for driving a d.c. motor with radio control comprising a receiving circuit for receiving and detecting certain signals transmitted from a transmitter, an amplifier for amplifying an output signal of said receiving circuit, a peak detector for converting the said amplified audio signal into a d.c. voltage, a comparator which have a hysteresis character dependent on the output level of the peak detector, a voltage regulating circuit supplying a stabilized voltage into all other components, and a direction control circuit to generate logic control signals deciding actual operation mode of the d.c. motor and motor driving circuits to produce motor driving signals by the output signal of the direction control circuit.