Abstract: A page in, burst-out FIFO buffer that stores only words in a single page and transfers the words to a DRAM utilizing a page mode transfer to increase data throughput and decrease latency offloading DRAM bandwidth.

Abstract: A current clamping circuit is provided which clamps a current signal to a predetermined reference current level. An input current signal and a reference current signal are supplied to the clamping circuit. The clamping circuit includes a current differencing device which determines the difference between the input current signal and the reference current signal. This current difference is summed with the original input current signal or a mirror thereof at a summing node to produce an output signal which is clamped at the predetermined reference current level.

Abstract: A duty cycle converter is provided for converting a pulsed input signal exhibiting a first duty cycle to a pulsed output signal exhibiting a second duty cycle. The converter includes an output pulse generator which synchronizes the leading edge of each output pulse with the leading edge of each input pulse. A first capacitor is charged to a first voltage level in response to a first input pulse. A second capacitor is switchably coupled to the first capacitor and, in response to a second input pulse, causes the voltage across the first capacitor to decrease to a second voltage level. A third capacitor is charged to the first voltage level in response to the second input pulse. A comparator determines when the voltage on the third capacitor increases to become equal to the second voltage level on the first capacitor.

Abstract: A keyboard interface controller in the nature of a state machine is placed in a stop mode or an idle mode after initialization. In stop or idle mode, all the keyboard conductors associated with the X-axis are activated, while all keyboard conductors associated with the Y-axis are sensed. Upon being awakened by an interrupt upon key closure from which the Y-axis location of the closed key is determined, the controller sequences through the steps of (a) determining the X-axis of the keyboard by activating the determined Y-axis conductor and sensing the X-axis conductors; (b) converting the crosspoint to a unique code; (c) transmitting the crosspoint code to the host; and (d) checking for either another closure or the release of the closure detected. When all keys are released, the controller returns to stop or idle mode.

Abstract: A frame buffer including a plurality of array planes of memory cells, row decoding circuitry for selecting rows of memory cells in each of the array planes to be accessed, column decoding circuitry for selecting columns of memory cells in each of the array planes to be accessed, a plurality of bitlines associated with the columns of memory cells of each array plane, each of the bitlines connecting to a column of memory cells and including a bitline sensing amplifier and a column select switch for providing access to the memory cells of that column of the array plane, a plurality of output sense amplifiers adapted to be connected to a selected number of bitlines in an array plane by closing of particular ones of the column select switches in the bitlines, first apparatus for providing output signals from the plurality of output sense amplifiers associated with each array plane to a data bus, and second apparatus for providing output signals from the plurality of output sense amplifiers associated with each arr

Abstract: A circuit for converting an input signal with an arbitrary duty cycle to an output signal with a 50 percent duty cycle. A bandpass filter removes unwanted DC and high frequency components from the input signal. A comparator compares the filtered signal to a reference voltage and provides very high gain amplification to produce an output signal having a 50 percent duty cycle. In one embodiment, two bandpass filters are used to condition the signal prior to providing it to the comparator. Each bandpass stage is comprised of a low pass filter followed by a high pass filter.

Abstract: A process for manufacturing an integrated circuit having both field effect and bipolar transistors provides, in one embodiment, a polycide film over the gate and field oxides. The polycide film is patterned such that a protective structure of gate material is formed on top the base region while the gate of the FET is formed, in a single process step. Ionic species are implanted to form the source and drain and the collector contact. The protective structure of gate material in the active region of the bipolar transistor is removed just before the base region is implanted to form the base. In a second embodiment, a silicon nitride oxidation mask for field oxide regions is formed over the bipolar transistor and the field effect transistor active regions. The portion of the nitride oxidation mask is removed only from the FET active regions after field oxide regions are formed.

Abstract: A programmable output driver circuit is provided having multiple drive capabilities for optimising noise margins at different frequencies. Several signal paths are designed in parallel, each comprising a driver unit made up of a pull-down and a pull-up transistor. Some of the paths can be disabled by NAND gates slowing down the driver circuit to reduce the attendant noise at lower frequencies. Different types of parallel structures can be designed, allowing for variable rise and fall times of the output signal, as well as skewed duty cycles.

Abstract: A process for manufacturing both field effect and bipolar transistors provides, in one embodiment, a polycide film over the gate and field oxides on the surface of the semiconductor substrate is patterned such that a protective structure of gate material is formed on top the base region of the bipolar transistor while the gate of the FET is formed. The channel region of the FET is defined by the gate, which also serves as a mask for etching away the gate oxide from the source and drain regions. The protective structure of gate material in the active region of the bipolar transistor is removed just before implantation to form the base of the bipolar transistor. In a second embodiment a silicon nitride oxidation mask for formation of filed oxide regions over the bipolar transistor and the FET active regions is formed and portions of the nitride oxidation mask is removed only from the FET active regions after field oxide regions are formed.

Abstract: A reference circuit for supplying current to high speed logic elements in an integrated circuit supplies less current when circuit temperature decreases while a supply voltage remains constant. The reference circuit supplies less current when the supply voltage increases while circuit temperature remains constant. A resistance with a temperature coefficient, in some embodiments a negative temperature coefficient, is used to decrease current flow in a first leg of an output mirror when temperature decreases. A feedback circuit is used to decrease current flow in the first leg of the output current mirror when the feedback circuit senses an increase in supply voltage by sensing a voltage change on a common control node of the output current mirror. The reference circuit sees many applications including supplying current to logic gates, input/output buffers, and sense amplifiers.

Abstract: Stored data elements are read from a first-in-first-out (FIFO) buffer memory in a pipelined fashion. A look-ahead fetching technique is utilized during a memory read cycle operation to advance (select) a subsequent data element in preparation for a next read command. Data read in advance is not output, however, until a subsequent read cycle corresponding to a next request for data in the buffer memory. A first data element written into the buffer memory is stored in an initial data register. Upon a first read request, the first data element is output from the initial data register. A first and a second memory array are provided for alternately storing successive ones of data elements written into the buffer memory. While a presently requested data element from the first array is being output, a memory cell in the second array, which contains the next data element to be requested, is selected and sensed, and the sensed value placed on an output line.

Abstract: A programmable buffer chip and programming method therefor are provided in which program information is entered into the buffer chip during a time period appended to the end of an ordinary reset period and so disguised as an extension of the reset period. Program information determines the buffer status conditions to be monitored at buffer status pins, and includes first offset data and a second offset data. A non-zero value in the first offset data indicates an offset defining an almost-full condition to be monitored. A non-zero value in the second offset data indicates an offset defining an almost-empty condition to be monitored. A program indicator bit in the program information indicates whether the buffer half-full condition, or both the full and the empty condition will be monitored at a particulat buffer status pin. The buffer is programmed by first causing the buffer chip to enter a reset mode, and then entering the program information in a disguised reset period following the actual reset period.

Abstract: A crystal oscillator circuit has a sleep mode of operation that reduces power consumption while maintaining oscillation to provide for a fast transition to a normal mode of operation.

Abstract: An output buffer with a controlled high logic state prevents the output voltage from increasing when the supply voltage, Vcc, increases. A fast low-to-high logic transition is achieved by using a pumping circuit to improve the low-to-high transition rate. However, when the Vcc voltage rises past a threshold value, the pumping circuit will only be enabled during a portion of the transition time. This prevents the output level from increasing beyond its nominal value. Because the output voltage is controlled, the high-to-low transition time is reduced and the ground bounce or noise generated by the output signal is minimized.

Abstract: In a noninverting Bi-CMOS gate, one or more passgates are utilized in the control path leading to a bipolar output transistor which switches the output of the Bi-CMOS gate. The control gate of one of the MOS transistors of a passgate is connected to an input signal of the Bi-CMOS gate. The control gate of the other MOS transistor is connected to the complement of the input signal. The output of the passgate is connected to the base of the bipolar output transistor. More than one such passgate connected to an input signal and its complement can be used. If multiple passgates are used, the outputs of the passgates may be tied together. This technique, utilizing the switching of the passgates with the input signals and their complements, is employed to create a family of Bi-CMOS noninverting gates such as buffers and AND gates. The propagation delay through the noninverting Bi-CMOS gates of the present invention are roughly equal to the propagation delay of a single Bi-CMOS inverter.

Abstract: A programmable interconnect device particularly suitable for field programmable ROM, field programmable gate array and field programmable microprocessor code, includes an intrinsic polycrystalline antifuse dielectric layer.

Abstract: The interconnect system of the present invention is comprised of a TiW metal barrier layer as well as a Ti metal barrier layer deposited on the silicon surface. An anisotropic etch process for the Ti/TiW/Al metal sandwich has also been developed without corrosion and metal residue. The addition of the Ti layer between the TiW layer and the silicon surface reduces the contact resistance between the metal and P.sup.+ silicon contact. This Ti layer also effectively improves the blocking of aluminum migration to the silicon surface through TiW grain boundaries. In order to realize good ohmic metal-P.sup.+ contacts, the surface concentration of the silicon should be very high. Therefore, the present invention also employs a plasma mode etch which removes about 250 .ANG. silicon since peak concentrations of P.sup.+ dopants (boron) are often found about 400 .ANG. below the silicon surface. This plasma mode etch will also remove silicon damage caused by previous etching.

Abstract: An intermediate Dc voltage generator providing low standby current. The present invention is a CMOS-based integrated circuit that generates a reference voltage level. The present invention accomplishes this task while also minimizing power consumption allowing application for portable computers or other battery-operated devices. The present invention replaces the second stage transistors of the prior art with transistors that have channel lengths greater than the channel lengths of the first stage transistors. This increases the turn on voltage of the second stage transistors. In addition, the channel width of the second stage transistors is less than the channel width of the first stage transistors further increasing turn on voltage. In this way, the second stage transistors are off, reducing the switching current and standby current contributed by the driver transistors at second stage, and providing intermediate level voltage references.

Abstract: A process to reduce M1/N+ contact resistance includes a low temperature anneal step, after the aluminum interconnect is alloyed at 400.degree. C. During the low temperature anneal step, the temperature of the furnace tube is lowered from 400.degree. C. to 250.degree. C. over a period of two hours, after which the integrated circuit is annealed under nitrogen for a further period of one hour. Alternately, the low temperature anneal is performed in an oven filled with nitrogen for a period of two hours at 250.degree. C.

Abstract: A charge pump having gate control voltages multiplexed to gates of FET driver circuits to precisely control charge injected by the charge pump to a low pass filter network. Large capacitors between the supply voltages and the respective gate control voltage derived from the particular supply voltage provide greater noise immunity which further reduces phase errors introduced by injected charge variations. The large capacitors help to hold the gate voltages constant, further controlling the injected charge.