Abstract: A multilayer ceramic capacitor includes: a ceramic body in which dielectric layers and first and second internal electrodes are alternately stacked; and first and second external electrodes formed on an outer surface of the ceramic body and electrically connected to the first and second internal electrodes, respectively. In a microstructure of the dielectric layer, dielectric grains are divided by a dielectric grain size into sections each having an interval of 50 nm, respectively, a fraction of the dielectric grains in each of the sections within a range of 50 nm to 450 nm is within a range of 0.025 to 0.20, and a thickness of the dielectric layer is 0.8 ?m or less.

Abstract: A method and a system for validating a temperature sensor integrated into a battery system are disclosed. In one aspect, the method includes determining an internal resistance of at least one battery cell in thermal contact with the temperature sensor and determining a state of charge (SOC) of the at least one battery cell. The method also includes determining at least one reference temperature from a lookup table (LUT) or a functional relationship connecting the internal resistance, the SOC, and a temperature of a reference battery cell. The method further includes comparing the at least one reference temperature with at least one temperature measurement of the temperature sensor to determine a difference therebetween. The method additionally includes validating the temperature sensor based on whether the difference exceeds a preconfigured threshold.

Abstract: Disclosed is an electronic device, which includes a display panel, a data driving circuit, a scan driving circuit, a signal control circuit, and a power supply circuit that trims a first voltage and a second voltage based on a first control value generated based on the first voltage and the second voltage, and the power supply circuit includes a controller that generates the first control value, a sign determining circuit that determines a sign of the first control value based on the first voltage and the second voltage, a plurality of voltage generators that generate a trimming voltage of the first control value based on the first voltage and the second voltage, and a first memory that stores the first control value, and the first control value is a value for controlling the sign determining circuit and each of the plurality of voltage generators.

Abstract: A display device includes a display panel including unit pixel areas and an input sensor including first-line elements and second-line elements defining crossing areas with the first-line elements. First group elements among the first-line elements and the second-line elements are electrically connected to each other to define a first electrode. Second group elements among the first-line elements and the second-line elements are electrically connected to each other to define a second electrode, and the second electrode is insulated from the first electrode while crossing the first electrode. A first angle defined by a first direction and a second direction and a second angle defined in the crossing areas by the first-line elements and the second-line elements to correspond to the first angle are different from each other.

Abstract: An electronic device includes: a display layer; a sensor layer on the display layer and comprising an active area and a peripheral area, the sensor layer being configured to operate in a first mode and a second mode different from the first mode; and a sensor controller configured to control the sensor layer, wherein the first mode comprises a first operation period, the second mode comprises a plurality of second operation periods and a third operation period, and the sensor controller is configured to sense a first input generated by a touch in the first operation period, to sense a second input generated by an input device in one of the second operation periods, to sense a third input generated by a touch different from the touch generating the first input in a portion of the active area in the third operation period, and to calculate a first sensing value.

Abstract: A phase-change memory device and a dynamic resistance drift compensation method thereof are provided. The phase-change memory device includes a plurality of bit lines; a plurality of source lines crossing the plurality of bit lines; a plurality of memory cells at respective intersections between the plurality of bit lines and the plurality of source lines, the plurality of memory cells each including a phase-change layer; a current generator connected to the plurality of bit lines and configured to generate a set current to be supplied to each of the plurality of memory cells; and a control driver configured to control the current generator and the plurality of bit lines to supply the set current to each of the plurality of memory cells.

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). An operating method of a policy control function (PCF) node in a wireless communication system, according to various embodiments of the present disclosure, comprises the steps of: determining, on the basis of preset conditions, whether to transmit a user equipment (UE) policy; transmitting a message including the UE policy; and receiving information related to a result of a policy section (PS) operation performed by a UE on the basis of the UE policy.

Abstract: A quantization apparatus comprises: a first quantization module for performing quantization without an inter-frame prediction; and a second quantization module for performing quantization with an inter-frame prediction, and the first quantization module comprises: a first quantization part for quantizing an input signal; and a third quantization part for quantizing a first quantization error signal, and the second quantization module comprises: a second quantization part for quantizing a prediction error; and a fourth quantization part for quantizing a second quantization error signal, and the first quantization part and the second quantization part comprise a trellis structured vector quantizer.

Abstract: An integrated circuit for a physically unclonable function (PUF) includes a controller configured to generate a control signal with reference to an address table, the address table representing a first mapping relationship between a first PUF cell group and a second PUF cell group having a first predetermined mismatch distance in relation to a PUF cell characteristic, and representing a second mapping relationship between a third PUF cell group and a fourth PUF cell group having a second predetermined mismatch distance in relation to the PUF cell characteristic; and a PUF block configured to provide PUF cell data groups in accordance with the first and second mapping relationships to the controller, in response to the control signal. The controller may be configured to generate an authentication key by respectively comparing the PUF cell data groups with reference data groups.

Abstract: A display panel includes pixels connected to first and second data lines and a readout line. The data driver supplies data signals to the first and second data lines and supplies an initialization voltage to the readout line. Each of the pixels includes at least one light emitting element and a driving transistor. The driving transistor controls an amount of current based on a difference between a corresponding data signal among the data signals and an initialization voltage. In a sensing mode, the data driver supplies a test voltage to the first data line and a first off voltage to the second data line in a first period and supplies a second off voltage to the second data line in a second period after the first period. The second off voltage is different from the test voltage and the first off voltage.

Abstract: Disclosed is a semiconductor package comprising a substrate, a chip stack including semiconductor chips stacked in an ascending stepwise shape on the substrate, first power/ground wires through which the substrate is connected to a lowermost semiconductor chip of the chip stack and neighboring semiconductor chips of the chip stack are connected to each other, and a second power/ground wire that extends from a first semiconductor chip and is connected to the substrate. The first semiconductor chip is one semiconductor chip other than the lowermost semiconductor chip and an uppermost semiconductor chip of the chip stack. The chip stack includes a first stack and a second stack on the first stack. The second stack constitutes a channel separate from that of the first stack.

Abstract: A display device includes a display panel including a first area and a second area. A support module includes a first support layer disposed on a bottom of the display panel and overlapping the first area and the second area. A second support layer is disposed on a bottom of the first support layer, overlapping the second area, and not overlapping the first area. The first support layer includes first joints overlapping the second area, and a plate overlapping the first area. The second support layer includes second joints. Each of the second joints is disposed on a bottom surface of each of the first joints, and a width of each of the second joints is narrower than a width of each of the first joints.

Abstract: An all-solid-state battery includes a body including a solid electrolyte layer, and an anode layer and a cathode layer alternately stacked with the solid electrolyte layer interposed therebetween. A first external electrode is disposed on one side of the body and includes a first electrode layer and a first conductive resin layer disposed on the first electrode layer, and a second external electrode is disposed on another side of the body and includes a second electrode layer and a second conductive resin layer disposed on the second electrode layer. A protective layer is disposed on an entirety of an external surface of the body free of the first and second electrode layers and on the first and second electrode layers, and at least one opening is included in a region of the protective layer disposed on at least one of the first electrode layer and the second electrode layer.

Abstract: A method for a remote support service performed by a remote control device includes receiving, from a controlled terminal, a first image packet including image data for a first image, rendering the first image based on the image data, transmitting a control packet including control data corresponding to an administrator's input to the controlled terminal when the administrator's input for the rendered first image is detected, receiving a second image packet including image data for a second image obtained by capturing the screen of the controlled terminal and identification information on whether or not the second image data is an image generated for the first time after a control event based on the control data is performed, determining whether or not to render the second image based on the identification information, and rendering the second image based on the image data for the second image according to the determination result.

Abstract: Apparatuses and methods for enhancement to standalone operation for higher frequency range in a wireless communication system. A method includes receiving a synchronization signals and physical broadcast channel (SS/PBCH) block and determining a set of configurations for a control resource set (CORESET #0) to receive a Type0 physical downlink control channel (Type0-PDCCH). The set of configurations includes a multiplexing pattern between the CORESET #0 and the SS/PBCH block; a number NRBCORESET #0 of resource blocks (RBs) for the CORESET #0; a number NsymbolCORESET #0 of symbols for the CORESET #0; and a frequency offset between the CORESET #0 and the SS/PBCH block. For a first multiplexing pattern between the CORESET #0 and the SS/PBCH block, the frequency offset between the CORESET #0 and the SS/PBCH block is determined as one of 0, NRBCORESET #0?NRBSSB, or (NRBCORESET #0?NRBSSB)/2.

Abstract: A method includes obtaining at least one image and a ground truth map associated with the at least one image. The method also includes generating multiple optical maps using multiple algorithms and the at least one image. The method further includes, for each algorithm, identifying at least one score for the algorithm using one or more of the optical maps generated using the algorithm and the ground truth map. The ground truth map identifies one or more boundaries associated with one or more foreground objects in the at least one image. The scores identify how well the optical maps generated using the algorithms separate the one or more foreground objects from a background in the at least one image.

Abstract: A cadmium free quantum dot not including cadmium and including: a semiconductor nanocrystal core comprising indium and phosphorous, a first semiconductor nanocrystal shell disposed on the semiconductor nanocrystal core and comprising zinc and selenium, and a second semiconductor nanocrystal shell disposed on the first semiconductor nanocrystal shell and comprising zinc and sulfur, a composition and composite including the same, and an electronic device.

Abstract: Provided is a display module including a substrate including a mounting surface, a side surface, and a chamfer portion formed between the mounting surface and the side surface, a plurality of inorganic light emitting diodes mounted on the mounting surface and each including a pair of electrodes electrically connected to the substrate, a black matrix arranged between the plurality of inorganic light emitting diodes, and a cover bonded to the mounting surface and configured to cover the mounting surface, wherein the pair of electrodes are oriented in a direction opposite to a direction in which the plurality of inorganic light emitting diodes emits light, and the cover is provided to extend outward of the side surface in an extension direction of the mounting surface.

Abstract: A display device includes first and second signal lines, first and second signal pads, and a pad insulating layer overlapping with the first and second signal lines. The first signal pad includes an intermediate conductive pattern overlapping with and connected to an end portion of the first signal line, and an upper conductive pattern on the intermediate conductive pattern, the upper conductive pattern being exposed through the pad insulating layer. The intermediate conductive pattern includes a first portion overlapping with the end portion of the first signal line, and a second portion between the end portion of the first signal line and an end portion of the second signal line and extending from the first portion. The upper conductive pattern is connected to the second portion of the intermediate conductive pattern.